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![Viresh Kumar](/assets/img/avatar_default.png)
This patch updates dev_pm_opp_find_freq_*() routines to get a reference to the OPPs returned by them. Also updates the users of dev_pm_opp_find_freq_*() routines to call dev_pm_opp_put() after they are done using the OPPs. As it is guaranteed the that OPPs wouldn't get freed while being used, the RCU read side locking present with the users isn't required anymore. Drop it as well. This patch also updates all users of devfreq_recommended_opp() which was returning an OPP received from the OPP core. Note that some of the OPP core routines have gained rcu_read_{lock|unlock}() calls, as those still use RCU specific APIs within them. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> [Devfreq] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
463 lines
13 KiB
C
463 lines
13 KiB
C
/*
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* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
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* Author: Lin Huang <hl@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/arm-smccc.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/devfreq.h>
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#include <linux/devfreq-event.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/regulator/consumer.h>
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#include <linux/rwsem.h>
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#include <linux/suspend.h>
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#include <soc/rockchip/rockchip_sip.h>
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struct dram_timing {
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unsigned int ddr3_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int dram_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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};
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struct rk3399_dmcfreq {
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struct device *dev;
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struct devfreq *devfreq;
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struct devfreq_simple_ondemand_data ondemand_data;
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struct clk *dmc_clk;
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struct devfreq_event_dev *edev;
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struct mutex lock;
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struct dram_timing timing;
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/*
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* DDR Converser of Frequency (DCF) is used to implement DDR frequency
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* conversion without the participation of CPU, we will implement and
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* control it in arm trust firmware.
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*/
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wait_queue_head_t wait_dcf_queue;
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int irq;
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int wait_dcf_flag;
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struct regulator *vdd_center;
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unsigned long rate, target_rate;
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unsigned long volt, target_volt;
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};
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static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
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u32 flags)
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{
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struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
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struct dev_pm_opp *opp;
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unsigned long old_clk_rate = dmcfreq->rate;
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unsigned long target_volt, target_rate;
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int err;
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opp = devfreq_recommended_opp(dev, freq, flags);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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target_rate = dev_pm_opp_get_freq(opp);
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target_volt = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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if (dmcfreq->rate == target_rate)
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return 0;
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mutex_lock(&dmcfreq->lock);
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/*
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* If frequency scaling from low to high, adjust voltage first.
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* If frequency scaling from high to low, adjust frequency first.
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*/
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if (old_clk_rate < target_rate) {
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err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
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target_volt);
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if (err) {
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dev_err(dev, "Cannot to set voltage %lu uV\n",
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target_volt);
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goto out;
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}
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}
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dmcfreq->wait_dcf_flag = 1;
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err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
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if (err) {
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dev_err(dev, "Cannot to set frequency %lu (%d)\n",
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target_rate, err);
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regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
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dmcfreq->volt);
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goto out;
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}
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/*
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* Wait until bcf irq happen, it means freq scaling finish in
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* arm trust firmware, use 100ms as timeout time.
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*/
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if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
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!dmcfreq->wait_dcf_flag, HZ / 10))
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dev_warn(dev, "Timeout waiting for dcf interrupt\n");
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/*
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* Check the dpll rate,
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* There only two result we will get,
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* 1. Ddr frequency scaling fail, we still get the old rate.
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* 2. Ddr frequency scaling sucessful, we get the rate we set.
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*/
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dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
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/* If get the incorrect rate, set voltage to old value. */
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if (dmcfreq->rate != target_rate) {
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dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
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Current frequency %lu\n", target_rate, dmcfreq->rate);
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regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
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dmcfreq->volt);
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goto out;
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} else if (old_clk_rate > target_rate)
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err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
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target_volt);
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if (err)
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dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
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dmcfreq->rate = target_rate;
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dmcfreq->volt = target_volt;
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out:
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mutex_unlock(&dmcfreq->lock);
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return err;
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}
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static int rk3399_dmcfreq_get_dev_status(struct device *dev,
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struct devfreq_dev_status *stat)
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{
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struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
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struct devfreq_event_data edata;
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int ret = 0;
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ret = devfreq_event_get_event(dmcfreq->edev, &edata);
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if (ret < 0)
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return ret;
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stat->current_frequency = dmcfreq->rate;
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stat->busy_time = edata.load_count;
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stat->total_time = edata.total_count;
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return ret;
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}
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static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
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{
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struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
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*freq = dmcfreq->rate;
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return 0;
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}
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static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
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.polling_ms = 200,
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.target = rk3399_dmcfreq_target,
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.get_dev_status = rk3399_dmcfreq_get_dev_status,
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.get_cur_freq = rk3399_dmcfreq_get_cur_freq,
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};
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static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
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{
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struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
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int ret = 0;
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ret = devfreq_event_disable_edev(dmcfreq->edev);
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if (ret < 0) {
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dev_err(dev, "failed to disable the devfreq-event devices\n");
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return ret;
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}
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ret = devfreq_suspend_device(dmcfreq->devfreq);
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if (ret < 0) {
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dev_err(dev, "failed to suspend the devfreq devices\n");
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return ret;
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}
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return 0;
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}
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static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
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{
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struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
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int ret = 0;
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ret = devfreq_event_enable_edev(dmcfreq->edev);
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if (ret < 0) {
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dev_err(dev, "failed to enable the devfreq-event devices\n");
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return ret;
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}
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ret = devfreq_resume_device(dmcfreq->devfreq);
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if (ret < 0) {
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dev_err(dev, "failed to resume the devfreq devices\n");
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return ret;
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}
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return ret;
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}
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static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
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rk3399_dmcfreq_resume);
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static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
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{
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struct rk3399_dmcfreq *dmcfreq = dev_id;
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struct arm_smccc_res res;
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dmcfreq->wait_dcf_flag = 0;
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wake_up(&dmcfreq->wait_dcf_queue);
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/* Clear the DCF interrupt */
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
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0, 0, 0, 0, &res);
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return IRQ_HANDLED;
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}
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static int of_get_ddr_timings(struct dram_timing *timing,
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struct device_node *np)
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{
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int ret = 0;
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ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
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&timing->ddr3_speed_bin);
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ret |= of_property_read_u32(np, "rockchip,pd_idle",
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&timing->pd_idle);
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ret |= of_property_read_u32(np, "rockchip,sr_idle",
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&timing->sr_idle);
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ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
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&timing->sr_mc_gate_idle);
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ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
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&timing->srpd_lite_idle);
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ret |= of_property_read_u32(np, "rockchip,standby_idle",
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&timing->standby_idle);
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ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
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&timing->auto_pd_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
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&timing->dram_dll_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
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&timing->phy_dll_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
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&timing->ddr3_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
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&timing->ddr3_drv);
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ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
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&timing->ddr3_odt);
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ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
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&timing->phy_ddr3_ca_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
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&timing->phy_ddr3_dq_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
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&timing->phy_ddr3_odt);
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ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
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&timing->lpddr3_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
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&timing->lpddr3_drv);
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ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
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&timing->lpddr3_odt);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
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&timing->phy_lpddr3_ca_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
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&timing->phy_lpddr3_dq_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
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&timing->phy_lpddr3_odt);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
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&timing->lpddr4_odt_dis_freq);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
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&timing->lpddr4_drv);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
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&timing->lpddr4_dq_odt);
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ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
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&timing->lpddr4_ca_odt);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
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&timing->phy_lpddr4_ca_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
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&timing->phy_lpddr4_ck_cs_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
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&timing->phy_lpddr4_dq_drv);
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ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
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&timing->phy_lpddr4_odt);
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return ret;
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}
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static int rk3399_dmcfreq_probe(struct platform_device *pdev)
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{
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struct arm_smccc_res res;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct rk3399_dmcfreq *data;
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int ret, irq, index, size;
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uint32_t *timing;
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struct dev_pm_opp *opp;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
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return -EINVAL;
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}
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data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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mutex_init(&data->lock);
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data->vdd_center = devm_regulator_get(dev, "center");
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if (IS_ERR(data->vdd_center)) {
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dev_err(dev, "Cannot get the regulator \"center\"\n");
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return PTR_ERR(data->vdd_center);
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}
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data->dmc_clk = devm_clk_get(dev, "dmc_clk");
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if (IS_ERR(data->dmc_clk)) {
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dev_err(dev, "Cannot get the clk dmc_clk\n");
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return PTR_ERR(data->dmc_clk);
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};
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data->irq = irq;
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ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
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dev_name(dev), data);
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if (ret) {
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dev_err(dev, "Failed to request dmc irq: %d\n", ret);
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return ret;
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}
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init_waitqueue_head(&data->wait_dcf_queue);
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data->wait_dcf_flag = 0;
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data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
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if (IS_ERR(data->edev))
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return -EPROBE_DEFER;
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ret = devfreq_event_enable_edev(data->edev);
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if (ret < 0) {
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dev_err(dev, "failed to enable devfreq-event devices\n");
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return ret;
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}
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/*
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* Get dram timing and pass it to arm trust firmware,
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* the dram drvier in arm trust firmware will get these
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* timing and to do dram initial.
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*/
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if (!of_get_ddr_timings(&data->timing, np)) {
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timing = &data->timing.ddr3_speed_bin;
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size = sizeof(struct dram_timing) / 4;
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for (index = 0; index < size; index++) {
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
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ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
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0, 0, 0, 0, &res);
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if (res.a0) {
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dev_err(dev, "Failed to set dram param: %ld\n",
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res.a0);
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return -EINVAL;
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}
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}
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}
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_INIT,
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0, 0, 0, 0, &res);
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/*
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* We add a devfreq driver to our parent since it has a device tree node
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* with operating points.
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*/
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if (dev_pm_opp_of_add_table(dev)) {
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dev_err(dev, "Invalid operating-points in device tree.\n");
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return -EINVAL;
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}
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of_property_read_u32(np, "upthreshold",
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&data->ondemand_data.upthreshold);
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of_property_read_u32(np, "downdifferential",
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&data->ondemand_data.downdifferential);
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data->rate = clk_get_rate(data->dmc_clk);
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opp = devfreq_recommended_opp(dev, &data->rate, 0);
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if (IS_ERR(opp))
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return PTR_ERR(opp);
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data->rate = dev_pm_opp_get_freq(opp);
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data->volt = dev_pm_opp_get_voltage(opp);
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dev_pm_opp_put(opp);
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rk3399_devfreq_dmc_profile.initial_freq = data->rate;
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data->devfreq = devm_devfreq_add_device(dev,
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&rk3399_devfreq_dmc_profile,
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"simple_ondemand",
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&data->ondemand_data);
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if (IS_ERR(data->devfreq))
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|
return PTR_ERR(data->devfreq);
|
|
devm_devfreq_register_opp_notifier(dev, data->devfreq);
|
|
|
|
data->dev = dev;
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
|
|
{ .compatible = "rockchip,rk3399-dmc" },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match);
|
|
|
|
static struct platform_driver rk3399_dmcfreq_driver = {
|
|
.probe = rk3399_dmcfreq_probe,
|
|
.driver = {
|
|
.name = "rk3399-dmc-freq",
|
|
.pm = &rk3399_dmcfreq_pm,
|
|
.of_match_table = rk3399dmc_devfreq_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(rk3399_dmcfreq_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
|
MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
|