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![Lukas Wunner](/assets/img/avatar_default.png)
Macs with Thunderbolt 1 do not have a unit-specific DROM: The DROM is empty with uid 0x1000000000000. (Apple started factory-burning a unit- specific DROM with Thunderbolt 2.) Instead, the NHI EFI driver supplies a DROM in a device property. Use it if available. It's only available when booting with the efistub. If it's not available, silently fall back to our hardcoded DROM. The size of the DROM is always 256 bytes. The number is hardcoded into the NHI EFI driver. This commit can deal with an arbitrary size however, just in case they ever change that. Background information: The EFI firmware volume contains ROM files for the NHI, GMUX and several other chips as well as key material. This strategy allows Apple to deploy ROM or key updates by simply publishing an EFI firmware update on their website. Drivers do not access those files directly but rather through a file server via EFI protocol AC5E4829-A8FD-440B-AF33-9FFE013B12D8. Files are identified by GUID, the NHI DROM has 339370BD-CFC6-4454-8EF7-704653120818. The NHI EFI driver amends that file with a unit-specific uid. The uid has 64 bit but its entropy is much lower: 24 bit represent the model, 24 bit are taken from a serial number, 16 bit are fixed. The NHI EFI driver obtains the serial number via the DataHub protocol, copies it into the DROM, calculates the CRC and submits the result as a device property. A modification is needed in the resume code where we currently read the uid of all switches in the hierarchy to detect plug events that occurred during sleep. On Thunderbolt 1 root switches this will now lead to a mismatch between the uid of the empty DROM and the EFI DROM. Exempt the root switch from this check: It's built in, so the uid should never change. However we continue to *read* the uid of the root switch, this seems like a good way to test its reachability after resume. Tested-by: Lukas Wunner <lukas@wunner.de> [MacBookPro9,1] Tested-by: Pierre Moreau <pierre.morrow@free.fr> [MacBookPro11,3] Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk> Acked-by: Andreas Noever <andreas.noever@gmail.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Pedro Vilaça <reverser@put.as> Cc: Peter Jones <pjones@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20161112213237.8804-10-matt@codeblueprint.co.uk Signed-off-by: Ingo Molnar <mingo@kernel.org>
498 lines
11 KiB
C
498 lines
11 KiB
C
/*
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* Thunderbolt Cactus Ridge driver - eeprom access
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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*/
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#include <linux/crc32.h>
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#include <linux/property.h>
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#include <linux/slab.h>
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#include "tb.h"
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/**
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* tb_eeprom_ctl_write() - write control word
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*/
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static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
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{
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return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
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}
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/**
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* tb_eeprom_ctl_write() - read control word
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*/
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static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
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{
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return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
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}
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enum tb_eeprom_transfer {
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TB_EEPROM_IN,
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TB_EEPROM_OUT,
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};
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/**
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* tb_eeprom_active - enable rom access
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*
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* WARNING: Always disable access after usage. Otherwise the controller will
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* fail to reprobe.
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*/
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static int tb_eeprom_active(struct tb_switch *sw, bool enable)
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{
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struct tb_eeprom_ctl ctl;
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int res = tb_eeprom_ctl_read(sw, &ctl);
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if (res)
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return res;
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if (enable) {
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ctl.access_high = 1;
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res = tb_eeprom_ctl_write(sw, &ctl);
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if (res)
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return res;
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ctl.access_low = 0;
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return tb_eeprom_ctl_write(sw, &ctl);
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} else {
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ctl.access_low = 1;
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res = tb_eeprom_ctl_write(sw, &ctl);
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if (res)
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return res;
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ctl.access_high = 0;
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return tb_eeprom_ctl_write(sw, &ctl);
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}
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}
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/**
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* tb_eeprom_transfer - transfer one bit
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*
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* If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
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* If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
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*/
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static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
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enum tb_eeprom_transfer direction)
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{
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int res;
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if (direction == TB_EEPROM_OUT) {
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res = tb_eeprom_ctl_write(sw, ctl);
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if (res)
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return res;
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}
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ctl->clock = 1;
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res = tb_eeprom_ctl_write(sw, ctl);
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if (res)
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return res;
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if (direction == TB_EEPROM_IN) {
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res = tb_eeprom_ctl_read(sw, ctl);
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if (res)
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return res;
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}
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ctl->clock = 0;
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return tb_eeprom_ctl_write(sw, ctl);
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}
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/**
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* tb_eeprom_out - write one byte to the bus
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*/
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static int tb_eeprom_out(struct tb_switch *sw, u8 val)
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{
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struct tb_eeprom_ctl ctl;
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int i;
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int res = tb_eeprom_ctl_read(sw, &ctl);
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if (res)
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return res;
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for (i = 0; i < 8; i++) {
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ctl.data_out = val & 0x80;
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res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
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if (res)
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return res;
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val <<= 1;
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}
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return 0;
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}
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/**
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* tb_eeprom_in - read one byte from the bus
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*/
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static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
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{
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struct tb_eeprom_ctl ctl;
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int i;
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int res = tb_eeprom_ctl_read(sw, &ctl);
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if (res)
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return res;
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*val = 0;
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for (i = 0; i < 8; i++) {
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*val <<= 1;
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res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
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if (res)
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return res;
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*val |= ctl.data_in;
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}
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return 0;
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}
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/**
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* tb_eeprom_read_n - read count bytes from offset into val
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*/
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static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
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size_t count)
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{
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int i, res;
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res = tb_eeprom_active(sw, true);
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if (res)
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return res;
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res = tb_eeprom_out(sw, 3);
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if (res)
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return res;
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res = tb_eeprom_out(sw, offset >> 8);
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if (res)
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return res;
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res = tb_eeprom_out(sw, offset);
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if (res)
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return res;
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for (i = 0; i < count; i++) {
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res = tb_eeprom_in(sw, val + i);
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if (res)
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return res;
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}
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return tb_eeprom_active(sw, false);
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}
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static u8 tb_crc8(u8 *data, int len)
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{
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int i, j;
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u8 val = 0xff;
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for (i = 0; i < len; i++) {
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val ^= data[i];
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for (j = 0; j < 8; j++)
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val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
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}
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return val;
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}
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static u32 tb_crc32(void *data, size_t len)
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{
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return ~__crc32c_le(~0, data, len);
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}
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#define TB_DROM_DATA_START 13
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struct tb_drom_header {
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/* BYTE 0 */
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u8 uid_crc8; /* checksum for uid */
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/* BYTES 1-8 */
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u64 uid;
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/* BYTES 9-12 */
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u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
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/* BYTE 13 */
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u8 device_rom_revision; /* should be <= 1 */
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u16 data_len:10;
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u8 __unknown1:6;
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/* BYTES 16-21 */
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u16 vendor_id;
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u16 model_id;
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u8 model_rev;
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u8 eeprom_rev;
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} __packed;
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enum tb_drom_entry_type {
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/* force unsigned to prevent "one-bit signed bitfield" warning */
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TB_DROM_ENTRY_GENERIC = 0U,
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TB_DROM_ENTRY_PORT,
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};
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struct tb_drom_entry_header {
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u8 len;
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u8 index:6;
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bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
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enum tb_drom_entry_type type:1;
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} __packed;
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struct tb_drom_entry_port {
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/* BYTES 0-1 */
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struct tb_drom_entry_header header;
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/* BYTE 2 */
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u8 dual_link_port_rid:4;
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u8 link_nr:1;
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u8 unknown1:2;
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bool has_dual_link_port:1;
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/* BYTE 3 */
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u8 dual_link_port_nr:6;
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u8 unknown2:2;
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/* BYTES 4 - 5 TODO decode */
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u8 micro2:4;
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u8 micro1:4;
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u8 micro3;
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/* BYTES 6-7, TODO: verify (find hardware that has these set) */
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u8 peer_port_rid:4;
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u8 unknown3:3;
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bool has_peer_port:1;
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u8 peer_port_nr:6;
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u8 unknown4:2;
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} __packed;
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/**
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* tb_eeprom_get_drom_offset - get drom offset within eeprom
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*/
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static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
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{
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struct tb_cap_plug_events cap;
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int res;
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if (!sw->cap_plug_events) {
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tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
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return -ENOSYS;
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}
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res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
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sizeof(cap) / 4);
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if (res)
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return res;
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if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
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tb_sw_warn(sw, "no NVM\n");
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return -ENOSYS;
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}
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if (cap.drom_offset > 0xffff) {
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tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
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cap.drom_offset);
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return -ENXIO;
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}
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*offset = cap.drom_offset;
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return 0;
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}
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/**
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* tb_drom_read_uid_only - read uid directly from drom
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*
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* Does not use the cached copy in sw->drom. Used during resume to check switch
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* identity.
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*/
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int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
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{
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u8 data[9];
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u16 drom_offset;
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u8 crc;
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int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
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if (res)
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return res;
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/* read uid */
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res = tb_eeprom_read_n(sw, drom_offset, data, 9);
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if (res)
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return res;
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crc = tb_crc8(data + 1, 8);
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if (crc != data[0]) {
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tb_sw_warn(sw, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
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data[0], crc);
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return -EIO;
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}
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*uid = *(u64 *)(data+1);
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return 0;
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}
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static void tb_drom_parse_port_entry(struct tb_port *port,
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struct tb_drom_entry_port *entry)
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{
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port->link_nr = entry->link_nr;
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if (entry->has_dual_link_port)
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port->dual_link_port =
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&port->sw->ports[entry->dual_link_port_nr];
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}
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static int tb_drom_parse_entry(struct tb_switch *sw,
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struct tb_drom_entry_header *header)
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{
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struct tb_port *port;
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int res;
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enum tb_port_type type;
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if (header->type != TB_DROM_ENTRY_PORT)
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return 0;
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port = &sw->ports[header->index];
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port->disabled = header->port_disabled;
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if (port->disabled)
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return 0;
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res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
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if (res)
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return res;
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type &= 0xffffff;
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if (type == TB_TYPE_PORT) {
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struct tb_drom_entry_port *entry = (void *) header;
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if (header->len != sizeof(*entry)) {
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tb_sw_warn(sw,
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"port entry has size %#x (expected %#zx)\n",
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header->len, sizeof(struct tb_drom_entry_port));
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return -EIO;
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}
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tb_drom_parse_port_entry(port, entry);
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}
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return 0;
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}
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/**
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* tb_drom_parse_entries - parse the linked list of drom entries
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*
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* Drom must have been copied to sw->drom.
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*/
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static int tb_drom_parse_entries(struct tb_switch *sw)
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{
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struct tb_drom_header *header = (void *) sw->drom;
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u16 pos = sizeof(*header);
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u16 drom_size = header->data_len + TB_DROM_DATA_START;
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while (pos < drom_size) {
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struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
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if (pos + 1 == drom_size || pos + entry->len > drom_size
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|| !entry->len) {
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tb_sw_warn(sw, "drom buffer overrun, aborting\n");
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return -EIO;
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}
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tb_drom_parse_entry(sw, entry);
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pos += entry->len;
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}
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return 0;
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}
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/**
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* tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
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*/
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static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
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{
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struct device *dev = &sw->tb->nhi->pdev->dev;
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int len, res;
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len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
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if (len < 0 || len < sizeof(struct tb_drom_header))
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return -EINVAL;
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sw->drom = kmalloc(len, GFP_KERNEL);
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if (!sw->drom)
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return -ENOMEM;
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res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
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len);
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if (res)
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goto err;
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*size = ((struct tb_drom_header *)sw->drom)->data_len +
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TB_DROM_DATA_START;
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if (*size > len)
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goto err;
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return 0;
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err:
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kfree(sw->drom);
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sw->drom = NULL;
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return -EINVAL;
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}
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/**
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* tb_drom_read - copy drom to sw->drom and parse it
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*/
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int tb_drom_read(struct tb_switch *sw)
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{
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u16 drom_offset;
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u16 size;
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u32 crc;
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struct tb_drom_header *header;
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int res;
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if (sw->drom)
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return 0;
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if (tb_route(sw) == 0) {
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/*
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* Apple's NHI EFI driver supplies a DROM for the root switch
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* in a device property. Use it if available.
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*/
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if (tb_drom_copy_efi(sw, &size) == 0)
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goto parse;
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/*
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* The root switch contains only a dummy drom (header only,
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* no entries). Hardcode the configuration here.
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*/
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tb_drom_read_uid_only(sw, &sw->uid);
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sw->ports[1].link_nr = 0;
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sw->ports[2].link_nr = 1;
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sw->ports[1].dual_link_port = &sw->ports[2];
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sw->ports[2].dual_link_port = &sw->ports[1];
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sw->ports[3].link_nr = 0;
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sw->ports[4].link_nr = 1;
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sw->ports[3].dual_link_port = &sw->ports[4];
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sw->ports[4].dual_link_port = &sw->ports[3];
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/* Port 5 is inaccessible on this gen 1 controller */
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if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
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sw->ports[5].disabled = true;
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return 0;
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}
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res = tb_eeprom_get_drom_offset(sw, &drom_offset);
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if (res)
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return res;
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res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
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if (res)
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return res;
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size &= 0x3ff;
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size += TB_DROM_DATA_START;
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tb_sw_info(sw, "reading drom (length: %#x)\n", size);
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if (size < sizeof(*header)) {
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tb_sw_warn(sw, "drom too small, aborting\n");
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return -EIO;
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}
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sw->drom = kzalloc(size, GFP_KERNEL);
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if (!sw->drom)
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return -ENOMEM;
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res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
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if (res)
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goto err;
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parse:
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header = (void *) sw->drom;
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if (header->data_len + TB_DROM_DATA_START != size) {
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tb_sw_warn(sw, "drom size mismatch, aborting\n");
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goto err;
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}
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crc = tb_crc8((u8 *) &header->uid, 8);
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if (crc != header->uid_crc8) {
|
|
tb_sw_warn(sw,
|
|
"drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
|
|
header->uid_crc8, crc);
|
|
goto err;
|
|
}
|
|
sw->uid = header->uid;
|
|
|
|
crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
|
|
if (crc != header->data_crc32) {
|
|
tb_sw_warn(sw,
|
|
"drom data crc32 mismatch (expected: %#x, got: %#x), aborting\n",
|
|
header->data_crc32, crc);
|
|
goto err;
|
|
}
|
|
|
|
if (header->device_rom_revision > 1)
|
|
tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
|
|
header->device_rom_revision);
|
|
|
|
return tb_drom_parse_entries(sw);
|
|
err:
|
|
kfree(sw->drom);
|
|
sw->drom = NULL;
|
|
return -EIO;
|
|
|
|
}
|