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368dd5acd1
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
97 lines
2.2 KiB
ArmAsm
97 lines
2.2 KiB
ArmAsm
/* SMP IPI low-level handler
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*
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* Copyright (C) 2006-2007 Matsushita Electric Industrial Co., Ltd.
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* All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/smp.h>
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#include <asm/system.h>
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#include <asm/thread_info.h>
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#include <asm/cpu-regs.h>
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#include <proc/smp-regs.h>
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#include <asm/asm-offsets.h>
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#include <asm/frame.inc>
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.am33_2
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###############################################################################
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#
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# IPI interrupt handler
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#
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###############################################################################
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.globl mn10300_low_ipi_handler
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mn10300_low_ipi_handler:
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add -4,sp
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mov d0,(sp)
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movhu (IAGR),d0
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and IAGR_GN,d0
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lsr 0x2,d0
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#ifdef CONFIG_MN10300_CACHE_ENABLED
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cmp FLUSH_CACHE_IPI,d0
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beq mn10300_flush_cache_ipi
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#endif
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cmp SMP_BOOT_IRQ,d0
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beq mn10300_smp_boot_ipi
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/* OTHERS */
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mov (sp),d0
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add 4,sp
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#ifdef CONFIG_GDBSTUB
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jmp gdbstub_io_rx_handler
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#else
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jmp end
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#endif
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###############################################################################
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#
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# Cache flush IPI interrupt handler
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#
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###############################################################################
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#ifdef CONFIG_MN10300_CACHE_ENABLED
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mn10300_flush_cache_ipi:
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mov (sp),d0
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add 4,sp
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/* FLUSH_CACHE_IPI */
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add -4,sp
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SAVE_ALL
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mov GxICR_DETECT,d2
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movbu d2,(GxICR(FLUSH_CACHE_IPI)) # ACK the interrupt
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movhu (GxICR(FLUSH_CACHE_IPI)),d2
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call smp_cache_interrupt[],0
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RESTORE_ALL
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jmp end
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#endif
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###############################################################################
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#
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# SMP boot CPU IPI interrupt handler
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#
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###############################################################################
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mn10300_smp_boot_ipi:
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/* clear interrupt */
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movhu (GxICR(SMP_BOOT_IRQ)),d0
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and ~GxICR_REQUEST,d0
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movhu d0,(GxICR(SMP_BOOT_IRQ))
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mov (sp),d0
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add 4,sp
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# get stack
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mov (CPUID),a0
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add -1,a0
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add a0,a0
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add a0,a0
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mov (start_stack,a0),a0
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mov a0,sp
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jmp initialize_secondary
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# Jump here after RTI to suppress the icache lookahead
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end:
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