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214 lines
5.5 KiB
C
214 lines
5.5 KiB
C
/*
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* pata_ninja32.c - Ninja32 PATA for new ATA layer
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* (C) 2007 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Note: The controller like many controllers has shared timings for
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* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
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* in the dma_stop function. Thus we actually don't need a set_dmamode
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* method as the PIO method is always called and will set the right PIO
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* timing parameters.
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*
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* The Ninja32 Cardbus is not a generic SFF controller. Instead it is
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* laid out as follows off BAR 0. This is based upon Mark Lord's delkin
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* driver and the extensive analysis done by the BSD developers, notably
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* ITOH Yasufumi.
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*
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* Base + 0x00 IRQ Status
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* Base + 0x01 IRQ control
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* Base + 0x02 Chipset control
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* Base + 0x04 VDMA and reset control + wait bits
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* Base + 0x08 BMIMBA
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* Base + 0x0C DMA Length
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* Base + 0x10 Taskfile
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* Base + 0x18 BMDMA Status ?
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* Base + 0x1C
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* Base + 0x1D Bus master control
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* bit 0 = enable
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* bit 1 = 0 write/1 read
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* bit 2 = 1 sgtable
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* bit 3 = go
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* bit 4-6 wait bits
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* bit 7 = done
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* Base + 0x1E AltStatus
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* Base + 0x1F timing register
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_ninja32"
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#define DRV_VERSION "0.0.1"
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/**
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* ninja32_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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static u16 pio_timing[5] = {
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0xd6, 0x85, 0x44, 0x33, 0x13
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};
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iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
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ap->ioaddr.bmdma_addr + 0x1f);
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ap->private_data = adev;
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}
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static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
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{
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struct ata_device *adev = &ap->link.device[device];
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if (ap->private_data != adev) {
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iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
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ata_std_dev_select(ap, device);
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ninja32_set_piomode(ap, adev);
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}
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}
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static struct scsi_host_template ninja32_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations ninja32_port_ops = {
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.set_piomode = ninja32_set_piomode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ninja32_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = ata_cable_40wire,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.port_start = ata_sff_port_start,
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};
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static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct ata_host *host;
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struct ata_port *ap;
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void __iomem *base;
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int rc;
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host = ata_host_alloc(&dev->dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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/* Set up the PCI device */
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rc = pcim_enable_device(dev);
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if (rc)
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return rc;
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rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
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if (rc == -EBUSY)
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pcim_pin_device(dev);
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if (rc)
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return rc;
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host->iomap = pcim_iomap_table(dev);
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rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
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if (rc)
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return rc;
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pci_set_master(dev);
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/* Set up the register mappings */
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base = host->iomap[0];
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if (!base)
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return -ENOMEM;
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ap->ops = &ninja32_port_ops;
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ap->pio_mask = 0x1F;
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ap->flags |= ATA_FLAG_SLAVE_POSS;
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ap->ioaddr.cmd_addr = base + 0x10;
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ap->ioaddr.ctl_addr = base + 0x1E;
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ap->ioaddr.altstatus_addr = base + 0x1E;
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ap->ioaddr.bmdma_addr = base;
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ata_std_ports(&ap->ioaddr);
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iowrite8(0x05, base + 0x01); /* Enable interrupt lines */
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iowrite8(0xB3, base + 0x02); /* Burst, ?? setup */
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iowrite8(0x00, base + 0x04); /* WAIT0 ? */
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/* FIXME: Should we disable them at remove ? */
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return ata_host_activate(host, dev->irq, ata_interrupt,
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IRQF_SHARED, &ninja32_sht);
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}
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static const struct pci_device_id ninja32[] = {
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{ 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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{ 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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{ },
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};
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static struct pci_driver ninja32_pci_driver = {
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.name = DRV_NAME,
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.id_table = ninja32,
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.probe = ninja32_init_one,
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.remove = ata_pci_remove_one
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};
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static int __init ninja32_init(void)
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{
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return pci_register_driver(&ninja32_pci_driver);
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}
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static void __exit ninja32_exit(void)
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{
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pci_unregister_driver(&ninja32_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, ninja32);
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MODULE_VERSION(DRV_VERSION);
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module_init(ninja32_init);
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module_exit(ninja32_exit);
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