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![Samuel Ortiz](/assets/img/avatar_default.png)
This is a patch for the Compaq ASIC3 multi function chip, found in many PDAs (iPAQs, HTCs...). It is a simplified version of Paul Sokolovsky's first proposal [1]. With this code, it is basically a GPIO and IRQ expander. My plan is to add more features once this patch gets reviewed and accepted. [1] http://lkml.org/lkml/2007/5/1/46 Signed-off-by: Samuel Ortiz <sameo@openedhand.com> Cc: Paul Sokolovsky <pmiscml@gmail.com> Cc: Ben Dooks <ben@trinity.fluff.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
588 lines
15 KiB
C
588 lines
15 KiB
C
/*
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* driver/mfd/asic3.c
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*
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* Compaq ASIC3 support.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Copyright 2001 Compaq Computer Corporation.
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* Copyright 2004-2005 Phil Blundell
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* Copyright 2007 OpenedHand Ltd.
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*
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* Authors: Phil Blundell <pb@handhelds.org>,
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* Samuel Ortiz <sameo@openedhand.com>
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*
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*/
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#include <linux/version.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/asic3.h>
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static inline void asic3_write_register(struct asic3 *asic,
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unsigned int reg, u32 value)
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{
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iowrite16(value, (unsigned long)asic->mapping +
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(reg >> asic->bus_shift));
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}
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static inline u32 asic3_read_register(struct asic3 *asic,
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unsigned int reg)
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{
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return ioread16((unsigned long)asic->mapping +
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(reg >> asic->bus_shift));
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}
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/* IRQs */
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#define MAX_ASIC_ISR_LOOPS 20
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#define ASIC3_GPIO_Base_INCR \
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(ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)
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static void asic3_irq_flip_edge(struct asic3 *asic,
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u32 base, int bit)
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{
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u16 edge;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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edge = asic3_read_register(asic,
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base + ASIC3_GPIO_EdgeTrigger);
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edge ^= bit;
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asic3_write_register(asic,
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base + ASIC3_GPIO_EdgeTrigger, edge);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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int iter, i;
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unsigned long flags;
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struct asic3 *asic;
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desc->chip->ack(irq);
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asic = desc->handler_data;
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for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
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u32 status;
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int bank;
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spin_lock_irqsave(&asic->lock, flags);
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status = asic3_read_register(asic,
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ASIC3_OFFSET(INTR, PIntStat));
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spin_unlock_irqrestore(&asic->lock, flags);
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/* Check all ten register bits */
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if ((status & 0x3ff) == 0)
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break;
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/* Handle GPIO IRQs */
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for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
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if (status & (1 << bank)) {
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unsigned long base, istat;
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base = ASIC3_GPIO_A_Base
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+ bank * ASIC3_GPIO_Base_INCR;
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spin_lock_irqsave(&asic->lock, flags);
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istat = asic3_read_register(asic,
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base +
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ASIC3_GPIO_IntStatus);
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/* Clearing IntStatus */
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asic3_write_register(asic,
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base +
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ASIC3_GPIO_IntStatus, 0);
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spin_unlock_irqrestore(&asic->lock, flags);
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for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
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int bit = (1 << i);
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unsigned int irqnr;
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if (!(istat & bit))
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continue;
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irqnr = asic->irq_base +
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(ASIC3_GPIOS_PER_BANK * bank)
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+ i;
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desc = irq_desc + irqnr;
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desc->handle_irq(irqnr, desc);
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if (asic->irq_bothedge[bank] & bit)
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asic3_irq_flip_edge(asic, base,
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bit);
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}
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}
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}
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/* Handle remaining IRQs in the status register */
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for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
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/* They start at bit 4 and go up */
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if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
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desc = irq_desc + + i;
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desc->handle_irq(asic->irq_base + i,
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desc);
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}
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}
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}
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if (iter >= MAX_ASIC_ISR_LOOPS)
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printk(KERN_ERR "%s: interrupt processing overrun\n",
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__FUNCTION__);
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}
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static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
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{
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int n;
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n = (irq - asic->irq_base) >> 4;
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return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base));
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}
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static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
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{
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return (irq - asic->irq_base) & 0xf;
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}
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static void asic3_mask_gpio_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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u32 val, bank, index;
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unsigned long flags;
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bank = asic3_irq_to_bank(asic, irq);
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index = asic3_irq_to_index(asic, irq);
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spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
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val |= 1 << index;
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asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_mask_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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int regval;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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regval = asic3_read_register(asic,
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ASIC3_INTR_Base +
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ASIC3_INTR_IntMask);
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regval &= ~(ASIC3_INTMASK_MASK0 <<
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(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
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asic3_write_register(asic,
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ASIC3_INTR_Base +
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ASIC3_INTR_IntMask,
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regval);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_unmask_gpio_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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u32 val, bank, index;
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unsigned long flags;
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bank = asic3_irq_to_bank(asic, irq);
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index = asic3_irq_to_index(asic, irq);
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spin_lock_irqsave(&asic->lock, flags);
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val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
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val &= ~(1 << index);
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asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static void asic3_unmask_irq(unsigned int irq)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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int regval;
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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regval = asic3_read_register(asic,
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ASIC3_INTR_Base +
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ASIC3_INTR_IntMask);
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regval |= (ASIC3_INTMASK_MASK0 <<
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(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
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asic3_write_register(asic,
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ASIC3_INTR_Base +
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ASIC3_INTR_IntMask,
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regval);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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struct asic3 *asic = get_irq_chip_data(irq);
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u32 bank, index;
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u16 trigger, level, edge, bit;
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unsigned long flags;
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bank = asic3_irq_to_bank(asic, irq);
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index = asic3_irq_to_index(asic, irq);
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bit = 1<<index;
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spin_lock_irqsave(&asic->lock, flags);
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level = asic3_read_register(asic,
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bank + ASIC3_GPIO_LevelTrigger);
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edge = asic3_read_register(asic,
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bank + ASIC3_GPIO_EdgeTrigger);
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trigger = asic3_read_register(asic,
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bank + ASIC3_GPIO_TriggerType);
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asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
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if (type == IRQT_RISING) {
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trigger |= bit;
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edge |= bit;
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} else if (type == IRQT_FALLING) {
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trigger |= bit;
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edge &= ~bit;
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} else if (type == IRQT_BOTHEDGE) {
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trigger |= bit;
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if (asic3_gpio_get_value(asic, irq - asic->irq_base))
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edge &= ~bit;
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else
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edge |= bit;
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asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
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} else if (type == IRQT_LOW) {
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trigger &= ~bit;
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level &= ~bit;
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} else if (type == IRQT_HIGH) {
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trigger &= ~bit;
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level |= bit;
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} else {
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/*
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* if type == IRQT_NOEDGE, we should mask interrupts, but
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* be careful to not unmask them if mask was also called.
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* Probably need internal state for mask.
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*/
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printk(KERN_NOTICE "asic3: irq type not changed.\n");
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}
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asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger,
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level);
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asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger,
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edge);
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asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType,
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trigger);
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spin_unlock_irqrestore(&asic->lock, flags);
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return 0;
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}
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static struct irq_chip asic3_gpio_irq_chip = {
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.name = "ASIC3-GPIO",
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.ack = asic3_mask_gpio_irq,
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.mask = asic3_mask_gpio_irq,
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.unmask = asic3_unmask_gpio_irq,
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.set_type = asic3_gpio_irq_type,
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};
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static struct irq_chip asic3_irq_chip = {
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.name = "ASIC3",
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.ack = asic3_mask_irq,
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.mask = asic3_mask_irq,
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.unmask = asic3_unmask_irq,
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};
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static int asic3_irq_probe(struct platform_device *pdev)
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{
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struct asic3 *asic = platform_get_drvdata(pdev);
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unsigned long clksel = 0;
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unsigned int irq, irq_base;
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asic->irq_nr = platform_get_irq(pdev, 0);
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if (asic->irq_nr < 0)
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return asic->irq_nr;
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/* turn on clock to IRQ controller */
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clksel |= CLOCK_SEL_CX;
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asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
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clksel);
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irq_base = asic->irq_base;
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for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
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if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
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set_irq_chip(irq, &asic3_gpio_irq_chip);
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else
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set_irq_chip(irq, &asic3_irq_chip);
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set_irq_chip_data(irq, asic);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask),
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ASIC3_INTMASK_GINTMASK);
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set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
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set_irq_type(asic->irq_nr, IRQT_RISING);
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set_irq_data(asic->irq_nr, asic);
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return 0;
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}
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static void asic3_irq_remove(struct platform_device *pdev)
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{
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struct asic3 *asic = platform_get_drvdata(pdev);
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unsigned int irq, irq_base;
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irq_base = asic->irq_base;
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for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
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set_irq_flags(irq, 0);
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set_irq_handler(irq, NULL);
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set_irq_chip(irq, NULL);
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set_irq_chip_data(irq, NULL);
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}
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set_irq_chained_handler(asic->irq_nr, NULL);
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}
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/* GPIOs */
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static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,
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unsigned int function)
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{
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return asic3_read_register(asic, base + function);
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}
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static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
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unsigned int function, u32 bits, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&asic->lock, flags);
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val |= (asic3_read_register(asic, base + function) & ~bits);
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asic3_write_register(asic, base + function, val);
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spin_unlock_irqrestore(&asic->lock, flags);
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}
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#define asic3_get_gpio_a(asic, fn) \
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asic3_get_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn)
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#define asic3_get_gpio_b(asic, fn) \
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asic3_get_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn)
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#define asic3_get_gpio_c(asic, fn) \
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asic3_get_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn)
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#define asic3_get_gpio_d(asic, fn) \
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asic3_get_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn)
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#define asic3_set_gpio_a(asic, fn, bits, val) \
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asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
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#define asic3_set_gpio_b(asic, fn, bits, val) \
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asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
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#define asic3_set_gpio_c(asic, fn, bits, val) \
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asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
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#define asic3_set_gpio_d(asic, fn, bits, val) \
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asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)
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#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \
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do { \
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asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
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asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
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asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
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asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
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} while (0)
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int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio)
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{
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u32 mask = ASIC3_GPIO_bit(gpio);
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switch (gpio >> 4) {
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case ASIC3_GPIO_BANK_A:
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return asic3_get_gpio_a(asic, Status) & mask;
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case ASIC3_GPIO_BANK_B:
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return asic3_get_gpio_b(asic, Status) & mask;
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case ASIC3_GPIO_BANK_C:
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return asic3_get_gpio_c(asic, Status) & mask;
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case ASIC3_GPIO_BANK_D:
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return asic3_get_gpio_d(asic, Status) & mask;
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default:
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printk(KERN_ERR "%s: invalid GPIO value 0x%x",
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__FUNCTION__, gpio);
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return -EINVAL;
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}
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}
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EXPORT_SYMBOL(asic3_gpio_get_value);
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void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val)
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{
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u32 mask = ASIC3_GPIO_bit(gpio);
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u32 bitval = 0;
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if (val)
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bitval = mask;
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switch (gpio >> 4) {
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case ASIC3_GPIO_BANK_A:
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asic3_set_gpio_a(asic, Out, mask, bitval);
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return;
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case ASIC3_GPIO_BANK_B:
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asic3_set_gpio_b(asic, Out, mask, bitval);
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return;
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case ASIC3_GPIO_BANK_C:
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asic3_set_gpio_c(asic, Out, mask, bitval);
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return;
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case ASIC3_GPIO_BANK_D:
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asic3_set_gpio_d(asic, Out, mask, bitval);
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return;
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default:
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printk(KERN_ERR "%s: invalid GPIO value 0x%x",
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__FUNCTION__, gpio);
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return;
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}
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}
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EXPORT_SYMBOL(asic3_gpio_set_value);
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static int asic3_gpio_probe(struct platform_device *pdev)
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{
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struct asic3_platform_data *pdata = pdev->dev.platform_data;
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struct asic3 *asic = platform_get_drvdata(pdev);
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asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
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asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
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asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
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asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);
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asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);
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asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);
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asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);
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asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);
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if (pdata) {
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asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);
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asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);
|
|
asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,
|
|
sleep_mask);
|
|
asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);
|
|
asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,
|
|
batt_fault_out);
|
|
asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,
|
|
sleep_conf);
|
|
asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,
|
|
alt_function);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void asic3_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
return;
|
|
}
|
|
|
|
|
|
/* Core */
|
|
static int asic3_probe(struct platform_device *pdev)
|
|
{
|
|
struct asic3_platform_data *pdata = pdev->dev.platform_data;
|
|
struct asic3 *asic;
|
|
struct resource *mem;
|
|
unsigned long clksel;
|
|
int ret;
|
|
|
|
asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
|
|
if (!asic)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&asic->lock);
|
|
platform_set_drvdata(pdev, asic);
|
|
asic->dev = &pdev->dev;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!mem) {
|
|
ret = -ENOMEM;
|
|
printk(KERN_ERR "asic3: no MEM resource\n");
|
|
goto err_out_1;
|
|
}
|
|
|
|
asic->mapping = ioremap(mem->start, PAGE_SIZE);
|
|
if (!asic->mapping) {
|
|
ret = -ENOMEM;
|
|
printk(KERN_ERR "asic3: couldn't ioremap\n");
|
|
goto err_out_1;
|
|
}
|
|
|
|
asic->irq_base = pdata->irq_base;
|
|
|
|
if (pdata && pdata->bus_shift)
|
|
asic->bus_shift = 2 - pdata->bus_shift;
|
|
else
|
|
asic->bus_shift = 0;
|
|
|
|
clksel = 0;
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
|
|
|
|
ret = asic3_irq_probe(pdev);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "asic3: couldn't probe IRQs\n");
|
|
goto err_out_2;
|
|
}
|
|
asic3_gpio_probe(pdev);
|
|
|
|
if (pdata->children) {
|
|
int i;
|
|
for (i = 0; i < pdata->n_children; i++) {
|
|
pdata->children[i]->dev.parent = &pdev->dev;
|
|
platform_device_register(pdata->children[i]);
|
|
}
|
|
}
|
|
|
|
printk(KERN_INFO "ASIC3 Core driver\n");
|
|
|
|
return 0;
|
|
|
|
err_out_2:
|
|
iounmap(asic->mapping);
|
|
err_out_1:
|
|
kfree(asic);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int asic3_remove(struct platform_device *pdev)
|
|
{
|
|
struct asic3 *asic = platform_get_drvdata(pdev);
|
|
|
|
asic3_gpio_remove(pdev);
|
|
asic3_irq_remove(pdev);
|
|
|
|
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
|
|
|
|
iounmap(asic->mapping);
|
|
|
|
kfree(asic);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void asic3_shutdown(struct platform_device *pdev)
|
|
{
|
|
}
|
|
|
|
static struct platform_driver asic3_device_driver = {
|
|
.driver = {
|
|
.name = "asic3",
|
|
},
|
|
.probe = asic3_probe,
|
|
.remove = __devexit_p(asic3_remove),
|
|
.shutdown = asic3_shutdown,
|
|
};
|
|
|
|
static int __init asic3_init(void)
|
|
{
|
|
int retval = 0;
|
|
retval = platform_driver_register(&asic3_device_driver);
|
|
return retval;
|
|
}
|
|
|
|
subsys_initcall(asic3_init);
|