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![Benjamin Gaignard](/assets/img/avatar_default.png)
Compositor control all the input sub-device (VID, GDP) and the mixer(s). It is the main entry point for composition. Layer interface is used to control the abstracted layers. Add debug in mixer and GDP. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
549 lines
14 KiB
C
549 lines
14 KiB
C
/*
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* Copyright (C) STMicroelectronics SA 2014
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* Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
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* Fabien Dessenne <fabien.dessenne@st.com>
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* for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include "sti_compositor.h"
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#include "sti_gdp.h"
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#include "sti_layer.h"
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#include "sti_vtg.h"
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#define ENA_COLOR_FILL BIT(8)
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#define WAIT_NEXT_VSYNC BIT(31)
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/* GDP color formats */
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#define GDP_RGB565 0x00
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#define GDP_RGB888 0x01
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#define GDP_RGB888_32 0x02
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#define GDP_ARGB8565 0x04
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#define GDP_ARGB8888 0x05
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#define GDP_ARGB1555 0x06
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#define GDP_ARGB4444 0x07
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#define GDP_CLUT8 0x0B
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#define GDP_YCBR888 0x10
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#define GDP_YCBR422R 0x12
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#define GDP_AYCBR8888 0x15
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#define GAM_GDP_CTL_OFFSET 0x00
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#define GAM_GDP_AGC_OFFSET 0x04
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#define GAM_GDP_VPO_OFFSET 0x0C
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#define GAM_GDP_VPS_OFFSET 0x10
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#define GAM_GDP_PML_OFFSET 0x14
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#define GAM_GDP_PMP_OFFSET 0x18
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#define GAM_GDP_SIZE_OFFSET 0x1C
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#define GAM_GDP_NVN_OFFSET 0x24
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#define GAM_GDP_KEY1_OFFSET 0x28
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#define GAM_GDP_KEY2_OFFSET 0x2C
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#define GAM_GDP_PPT_OFFSET 0x34
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#define GAM_GDP_CML_OFFSET 0x3C
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#define GAM_GDP_MST_OFFSET 0x68
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#define GAM_GDP_ALPHARANGE_255 BIT(5)
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#define GAM_GDP_AGC_FULL_RANGE 0x00808080
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#define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
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#define GAM_GDP_SIZE_MAX 0x7FF
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#define GDP_NODE_NB_BANK 2
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#define GDP_NODE_PER_FIELD 2
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struct sti_gdp_node {
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u32 gam_gdp_ctl;
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u32 gam_gdp_agc;
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u32 reserved1;
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u32 gam_gdp_vpo;
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u32 gam_gdp_vps;
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u32 gam_gdp_pml;
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u32 gam_gdp_pmp;
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u32 gam_gdp_size;
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u32 reserved2;
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u32 gam_gdp_nvn;
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u32 gam_gdp_key1;
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u32 gam_gdp_key2;
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u32 reserved3;
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u32 gam_gdp_ppt;
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u32 reserved4;
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u32 gam_gdp_cml;
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};
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struct sti_gdp_node_list {
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struct sti_gdp_node *top_field;
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struct sti_gdp_node *btm_field;
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};
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/**
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* STI GDP structure
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*
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* @layer: layer structure
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* @clk_pix: pixel clock for the current gdp
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* @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
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* @is_curr_top: true if the current node processed is the top field
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* @node_list: array of node list
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*/
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struct sti_gdp {
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struct sti_layer layer;
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struct clk *clk_pix;
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struct notifier_block vtg_field_nb;
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bool is_curr_top;
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struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
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};
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#define to_sti_gdp(x) container_of(x, struct sti_gdp, layer)
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static const uint32_t gdp_supported_formats[] = {
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_AYUV,
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DRM_FORMAT_YUV444,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_C8,
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};
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static const uint32_t *sti_gdp_get_formats(struct sti_layer *layer)
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{
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return gdp_supported_formats;
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}
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static unsigned int sti_gdp_get_nb_formats(struct sti_layer *layer)
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{
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return ARRAY_SIZE(gdp_supported_formats);
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}
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static int sti_gdp_fourcc2format(int fourcc)
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{
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switch (fourcc) {
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case DRM_FORMAT_XRGB8888:
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return GDP_RGB888_32;
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case DRM_FORMAT_ARGB8888:
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return GDP_ARGB8888;
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case DRM_FORMAT_ARGB4444:
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return GDP_ARGB4444;
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case DRM_FORMAT_ARGB1555:
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return GDP_ARGB1555;
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case DRM_FORMAT_RGB565:
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return GDP_RGB565;
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case DRM_FORMAT_RGB888:
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return GDP_RGB888;
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case DRM_FORMAT_AYUV:
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return GDP_AYCBR8888;
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case DRM_FORMAT_YUV444:
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return GDP_YCBR888;
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case DRM_FORMAT_VYUY:
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return GDP_YCBR422R;
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case DRM_FORMAT_C8:
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return GDP_CLUT8;
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}
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return -1;
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}
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static int sti_gdp_get_alpharange(int format)
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{
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switch (format) {
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case GDP_ARGB8565:
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case GDP_ARGB8888:
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case GDP_AYCBR8888:
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return GAM_GDP_ALPHARANGE_255;
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}
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return 0;
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}
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/**
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* sti_gdp_get_free_nodes
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* @layer: gdp layer
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*
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* Look for a GDP node list that is not currently read by the HW.
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*
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* RETURNS:
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* Pointer to the free GDP node list
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*/
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static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_layer *layer)
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{
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int hw_nvn;
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void *virt_nvn;
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struct sti_gdp *gdp = to_sti_gdp(layer);
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unsigned int i;
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hw_nvn = readl(layer->regs + GAM_GDP_NVN_OFFSET);
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if (!hw_nvn)
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goto end;
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virt_nvn = dma_to_virt(layer->dev, (dma_addr_t) hw_nvn);
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for (i = 0; i < GDP_NODE_NB_BANK; i++)
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if ((virt_nvn != gdp->node_list[i].btm_field) &&
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(virt_nvn != gdp->node_list[i].top_field))
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return &gdp->node_list[i];
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/* in hazardious cases restart with the first node */
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DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
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sti_layer_to_str(layer), hw_nvn);
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end:
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return &gdp->node_list[0];
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}
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/**
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* sti_gdp_get_current_nodes
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* @layer: GDP layer
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*
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* Look for GDP nodes that are currently read by the HW.
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*
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* RETURNS:
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* Pointer to the current GDP node list
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*/
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static
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struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_layer *layer)
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{
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int hw_nvn;
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void *virt_nvn;
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struct sti_gdp *gdp = to_sti_gdp(layer);
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unsigned int i;
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hw_nvn = readl(layer->regs + GAM_GDP_NVN_OFFSET);
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if (!hw_nvn)
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goto end;
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virt_nvn = dma_to_virt(layer->dev, (dma_addr_t) hw_nvn);
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for (i = 0; i < GDP_NODE_NB_BANK; i++)
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if ((virt_nvn == gdp->node_list[i].btm_field) ||
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(virt_nvn == gdp->node_list[i].top_field))
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return &gdp->node_list[i];
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end:
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DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
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hw_nvn, sti_layer_to_str(layer));
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return NULL;
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}
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/**
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* sti_gdp_prepare_layer
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* @lay: gdp layer
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* @first_prepare: true if it is the first time this function is called
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*
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* Update the free GDP node list according to the layer properties.
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*
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* RETURNS:
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* 0 on success.
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*/
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static int sti_gdp_prepare_layer(struct sti_layer *layer, bool first_prepare)
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{
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struct sti_gdp_node_list *list;
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struct sti_gdp_node *top_field, *btm_field;
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struct drm_display_mode *mode = layer->mode;
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struct device *dev = layer->dev;
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struct sti_gdp *gdp = to_sti_gdp(layer);
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struct sti_compositor *compo = dev_get_drvdata(dev);
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int format;
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unsigned int depth, bpp;
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int rate = mode->clock * 1000;
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int res;
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u32 ydo, xdo, yds, xds;
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list = sti_gdp_get_free_nodes(layer);
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top_field = list->top_field;
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btm_field = list->btm_field;
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dev_dbg(dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
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sti_layer_to_str(layer), top_field, btm_field);
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/* Build the top field from layer params */
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top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
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top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
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format = sti_gdp_fourcc2format(layer->format);
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if (format == -1) {
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DRM_ERROR("Format not supported by GDP %.4s\n",
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(char *)&layer->format);
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return 1;
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}
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top_field->gam_gdp_ctl |= format;
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top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
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top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
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/* pixel memory location */
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drm_fb_get_bpp_depth(layer->format, &depth, &bpp);
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top_field->gam_gdp_pml = (u32) layer->paddr + layer->offsets[0];
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top_field->gam_gdp_pml += layer->src_x * (bpp >> 3);
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top_field->gam_gdp_pml += layer->src_y * layer->pitches[0];
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/* input parameters */
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top_field->gam_gdp_pmp = layer->pitches[0];
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top_field->gam_gdp_size =
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clamp_val(layer->src_h, 0, GAM_GDP_SIZE_MAX) << 16 |
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clamp_val(layer->src_w, 0, GAM_GDP_SIZE_MAX);
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/* output parameters */
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ydo = sti_vtg_get_line_number(*mode, layer->dst_y);
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yds = sti_vtg_get_line_number(*mode, layer->dst_y + layer->dst_h - 1);
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xdo = sti_vtg_get_pixel_number(*mode, layer->dst_x);
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xds = sti_vtg_get_pixel_number(*mode, layer->dst_x + layer->dst_w - 1);
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top_field->gam_gdp_vpo = (ydo << 16) | xdo;
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top_field->gam_gdp_vps = (yds << 16) | xds;
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/* Same content and chained together */
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memcpy(btm_field, top_field, sizeof(*btm_field));
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top_field->gam_gdp_nvn = virt_to_dma(dev, btm_field);
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btm_field->gam_gdp_nvn = virt_to_dma(dev, top_field);
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/* Interlaced mode */
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if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE)
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btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
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layer->pitches[0];
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if (first_prepare) {
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/* Register gdp callback */
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if (sti_vtg_register_client(layer->mixer_id == STI_MIXER_MAIN ?
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compo->vtg_main : compo->vtg_aux,
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&gdp->vtg_field_nb, layer->mixer_id)) {
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DRM_ERROR("Cannot register VTG notifier\n");
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return 1;
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}
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/* Set and enable gdp clock */
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if (gdp->clk_pix) {
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res = clk_set_rate(gdp->clk_pix, rate);
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if (res < 0) {
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DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
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rate);
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return 1;
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}
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if (clk_prepare_enable(gdp->clk_pix)) {
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DRM_ERROR("Failed to prepare/enable gdp\n");
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return 1;
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}
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}
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}
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return 0;
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}
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/**
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* sti_gdp_commit_layer
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* @lay: gdp layer
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*
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* Update the NVN field of the 'right' field of the current GDP node (being
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* used by the HW) with the address of the updated ('free') top field GDP node.
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* - In interlaced mode the 'right' field is the bottom field as we update
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* frames starting from their top field
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* - In progressive mode, we update both bottom and top fields which are
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* equal nodes.
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* At the next VSYNC, the updated node list will be used by the HW.
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*
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* RETURNS:
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* 0 on success.
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*/
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static int sti_gdp_commit_layer(struct sti_layer *layer)
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{
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struct sti_gdp_node_list *updated_list = sti_gdp_get_free_nodes(layer);
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struct sti_gdp_node *updated_top_node = updated_list->top_field;
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struct sti_gdp_node *updated_btm_node = updated_list->btm_field;
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struct sti_gdp *gdp = to_sti_gdp(layer);
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u32 dma_updated_top = virt_to_dma(layer->dev, updated_top_node);
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u32 dma_updated_btm = virt_to_dma(layer->dev, updated_btm_node);
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struct sti_gdp_node_list *curr_list = sti_gdp_get_current_nodes(layer);
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dev_dbg(layer->dev, "%s %s top/btm_node:0x%p/0x%p\n", __func__,
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sti_layer_to_str(layer),
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updated_top_node, updated_btm_node);
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dev_dbg(layer->dev, "Current NVN:0x%X\n",
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readl(layer->regs + GAM_GDP_NVN_OFFSET));
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dev_dbg(layer->dev, "Posted buff: %lx current buff: %x\n",
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(unsigned long)layer->paddr,
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readl(layer->regs + GAM_GDP_PML_OFFSET));
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if (curr_list == NULL) {
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/* First update or invalid node should directly write in the
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* hw register */
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DRM_DEBUG_DRIVER("%s first update (or invalid node)",
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sti_layer_to_str(layer));
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writel(gdp->is_curr_top == true ?
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dma_updated_btm : dma_updated_top,
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layer->regs + GAM_GDP_NVN_OFFSET);
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return 0;
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}
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if (layer->mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (gdp->is_curr_top == true) {
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/* Do not update in the middle of the frame, but
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* postpone the update after the bottom field has
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* been displayed */
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curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
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} else {
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/* Direct update to avoid one frame delay */
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writel(dma_updated_top,
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layer->regs + GAM_GDP_NVN_OFFSET);
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}
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} else {
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/* Direct update for progressive to avoid one frame delay */
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writel(dma_updated_top, layer->regs + GAM_GDP_NVN_OFFSET);
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}
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return 0;
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}
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/**
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* sti_gdp_disable_layer
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* @lay: gdp layer
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*
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* Disable a GDP.
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*
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* RETURNS:
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* 0 on success.
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*/
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static int sti_gdp_disable_layer(struct sti_layer *layer)
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{
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unsigned int i;
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struct sti_gdp *gdp = to_sti_gdp(layer);
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struct sti_compositor *compo = dev_get_drvdata(layer->dev);
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DRM_DEBUG_DRIVER("%s\n", sti_layer_to_str(layer));
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/* Set the nodes as 'to be ignored on mixer' */
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for (i = 0; i < GDP_NODE_NB_BANK; i++) {
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gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
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gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
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}
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if (sti_vtg_unregister_client(layer->mixer_id == STI_MIXER_MAIN ?
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compo->vtg_main : compo->vtg_aux, &gdp->vtg_field_nb))
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DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
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if (gdp->clk_pix)
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clk_disable_unprepare(gdp->clk_pix);
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return 0;
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}
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/**
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* sti_gdp_field_cb
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* @nb: notifier block
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* @event: event message
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* @data: private data
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*
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* Handle VTG top field and bottom field event.
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*
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* RETURNS:
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* 0 on success.
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*/
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int sti_gdp_field_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
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switch (event) {
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case VTG_TOP_FIELD_EVENT:
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gdp->is_curr_top = true;
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break;
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case VTG_BOTTOM_FIELD_EVENT:
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gdp->is_curr_top = false;
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break;
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default:
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DRM_ERROR("unsupported event: %lu\n", event);
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break;
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}
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return 0;
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}
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static void sti_gdp_init(struct sti_layer *layer)
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{
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|
struct sti_gdp *gdp = to_sti_gdp(layer);
|
|
struct device_node *np = layer->dev->of_node;
|
|
dma_addr_t dma;
|
|
void *base;
|
|
unsigned int i, size;
|
|
|
|
/* Allocate all the nodes within a single memory page */
|
|
size = sizeof(struct sti_gdp_node) *
|
|
GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
|
|
|
|
base = dma_alloc_writecombine(layer->dev,
|
|
size, &dma, GFP_KERNEL | GFP_DMA);
|
|
if (!base) {
|
|
DRM_ERROR("Failed to allocate memory for GDP node\n");
|
|
return;
|
|
}
|
|
memset(base, 0, size);
|
|
|
|
for (i = 0; i < GDP_NODE_NB_BANK; i++) {
|
|
if (virt_to_dma(layer->dev, base) & 0xF) {
|
|
DRM_ERROR("Mem alignment failed\n");
|
|
return;
|
|
}
|
|
gdp->node_list[i].top_field = base;
|
|
DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
|
|
base += sizeof(struct sti_gdp_node);
|
|
|
|
if (virt_to_dma(layer->dev, base) & 0xF) {
|
|
DRM_ERROR("Mem alignment failed\n");
|
|
return;
|
|
}
|
|
gdp->node_list[i].btm_field = base;
|
|
DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
|
|
base += sizeof(struct sti_gdp_node);
|
|
}
|
|
|
|
if (of_device_is_compatible(np, "st,stih407-compositor")) {
|
|
/* GDP of STiH407 chip have its own pixel clock */
|
|
char *clk_name;
|
|
|
|
switch (layer->desc) {
|
|
case STI_GDP_0:
|
|
clk_name = "pix_gdp1";
|
|
break;
|
|
case STI_GDP_1:
|
|
clk_name = "pix_gdp2";
|
|
break;
|
|
case STI_GDP_2:
|
|
clk_name = "pix_gdp3";
|
|
break;
|
|
case STI_GDP_3:
|
|
clk_name = "pix_gdp4";
|
|
break;
|
|
default:
|
|
DRM_ERROR("GDP id not recognized\n");
|
|
return;
|
|
}
|
|
|
|
gdp->clk_pix = devm_clk_get(layer->dev, clk_name);
|
|
if (IS_ERR(gdp->clk_pix))
|
|
DRM_ERROR("Cannot get %s clock\n", clk_name);
|
|
}
|
|
}
|
|
|
|
static const struct sti_layer_funcs gdp_ops = {
|
|
.get_formats = sti_gdp_get_formats,
|
|
.get_nb_formats = sti_gdp_get_nb_formats,
|
|
.init = sti_gdp_init,
|
|
.prepare = sti_gdp_prepare_layer,
|
|
.commit = sti_gdp_commit_layer,
|
|
.disable = sti_gdp_disable_layer,
|
|
};
|
|
|
|
struct sti_layer *sti_gdp_create(struct device *dev, int id)
|
|
{
|
|
struct sti_gdp *gdp;
|
|
|
|
gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
|
|
if (!gdp) {
|
|
DRM_ERROR("Failed to allocate memory for GDP\n");
|
|
return NULL;
|
|
}
|
|
|
|
gdp->layer.ops = &gdp_ops;
|
|
gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
|
|
|
|
return (struct sti_layer *)gdp;
|
|
}
|