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synced 2024-08-26 02:39:48 +00:00
![Biju Das](/assets/img/avatar_default.png)
GPIO hole is present in RZ/G1C SoC. Valid GPIO pins on bank3 are in the range GP3_0 to GP3_16 and GP3_27 to GP3_29. The GPIO pins between GP3_17 to GP3_26 are unused. Add support for handling unused GPIO's. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
611 lines
16 KiB
C
611 lines
16 KiB
C
/*
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* Renesas R-Car GPIO Support
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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struct gpio_rcar_bank_info {
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u32 iointsel;
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u32 inoutsel;
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u32 outdt;
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u32 posneg;
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u32 edglevel;
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u32 bothedge;
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u32 intmsk;
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};
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struct gpio_rcar_priv {
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void __iomem *base;
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spinlock_t lock;
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struct platform_device *pdev;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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unsigned int irq_parent;
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atomic_t wakeup_path;
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bool has_both_edge_trigger;
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struct gpio_rcar_bank_info bank_info;
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};
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#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
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#define INOUTSEL 0x04 /* General Input/Output Switching Register */
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#define OUTDT 0x08 /* General Output Register */
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#define INDT 0x0c /* General Input Register */
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#define INTDT 0x10 /* Interrupt Display Register */
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#define INTCLR 0x14 /* Interrupt Clear Register */
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#define INTMSK 0x18 /* Interrupt Mask Register */
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#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
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#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
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#define EDGLEVEL 0x24 /* Edge/level Select Register */
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#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
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#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
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#define RCAR_MAX_GPIO_PER_BANK 32
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static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
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{
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return ioread32(p->base + offs);
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}
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static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
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u32 value)
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{
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iowrite32(value, p->base + offs);
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}
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static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
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int bit, bool value)
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{
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u32 tmp = gpio_rcar_read(p, offs);
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if (value)
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tmp |= BIT(bit);
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else
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tmp &= ~BIT(bit);
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gpio_rcar_write(p, offs, tmp);
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}
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static void gpio_rcar_irq_disable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_rcar_priv *p = gpiochip_get_data(gc);
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gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
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}
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static void gpio_rcar_irq_enable(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_rcar_priv *p = gpiochip_get_data(gc);
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gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
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}
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static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
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unsigned int hwirq,
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bool active_high_rising_edge,
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bool level_trigger,
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bool both)
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{
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unsigned long flags;
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/* follow steps in the GPIO documentation for
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* "Setting Edge-Sensitive Interrupt Input Mode" and
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* "Setting Level-Sensitive Interrupt Input Mode"
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*/
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spin_lock_irqsave(&p->lock, flags);
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/* Configure postive or negative logic in POSNEG */
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gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
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/* Configure edge or level trigger in EDGLEVEL */
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gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
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/* Select one edge or both edges in BOTHEDGE */
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if (p->has_both_edge_trigger)
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gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
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/* Select "Interrupt Input Mode" in IOINTSEL */
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gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
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/* Write INTCLR in case of edge trigger */
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if (!level_trigger)
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gpio_rcar_write(p, INTCLR, BIT(hwirq));
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_rcar_priv *p = gpiochip_get_data(gc);
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unsigned int hwirq = irqd_to_hwirq(d);
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dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
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false);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
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false);
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break;
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case IRQ_TYPE_EDGE_RISING:
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gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
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false);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
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false);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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if (!p->has_both_edge_trigger)
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return -EINVAL;
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gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
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true);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_rcar_priv *p = gpiochip_get_data(gc);
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int error;
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if (p->irq_parent) {
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error = irq_set_irq_wake(p->irq_parent, on);
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if (error) {
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dev_dbg(&p->pdev->dev,
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"irq %u doesn't support irq_set_wake\n",
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p->irq_parent);
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p->irq_parent = 0;
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}
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}
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if (on)
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atomic_inc(&p->wakeup_path);
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else
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atomic_dec(&p->wakeup_path);
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return 0;
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}
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static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
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{
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struct gpio_rcar_priv *p = dev_id;
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u32 pending;
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unsigned int offset, irqs_handled = 0;
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while ((pending = gpio_rcar_read(p, INTDT) &
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gpio_rcar_read(p, INTMSK))) {
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offset = __ffs(pending);
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gpio_rcar_write(p, INTCLR, BIT(offset));
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generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
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offset));
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irqs_handled++;
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}
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return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
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}
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static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
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unsigned int gpio,
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bool output)
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{
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struct gpio_rcar_priv *p = gpiochip_get_data(chip);
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unsigned long flags;
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/* follow steps in the GPIO documentation for
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* "Setting General Output Mode" and
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* "Setting General Input Mode"
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*/
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spin_lock_irqsave(&p->lock, flags);
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/* Configure postive logic in POSNEG */
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gpio_rcar_modify_bit(p, POSNEG, gpio, false);
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/* Select "General Input/Output Mode" in IOINTSEL */
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gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
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/* Select Input Mode or Output Mode in INOUTSEL */
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gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
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{
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struct gpio_rcar_priv *p = gpiochip_get_data(chip);
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int error;
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error = pm_runtime_get_sync(&p->pdev->dev);
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if (error < 0)
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return error;
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error = pinctrl_gpio_request(chip->base + offset);
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if (error)
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pm_runtime_put(&p->pdev->dev);
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return error;
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}
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static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
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{
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struct gpio_rcar_priv *p = gpiochip_get_data(chip);
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pinctrl_gpio_free(chip->base + offset);
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/*
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* Set the GPIO as an input to ensure that the next GPIO request won't
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* drive the GPIO pin as an output.
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*/
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gpio_rcar_config_general_input_output_mode(chip, offset, false);
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pm_runtime_put(&p->pdev->dev);
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}
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static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct gpio_rcar_priv *p = gpiochip_get_data(chip);
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return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
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}
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static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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gpio_rcar_config_general_input_output_mode(chip, offset, false);
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return 0;
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}
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static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
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{
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u32 bit = BIT(offset);
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/* testing on r8a7790 shows that INDT does not show correct pin state
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* when configured as output, so use OUTDT in case of output pins */
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if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
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return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
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else
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return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
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}
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static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct gpio_rcar_priv *p = gpiochip_get_data(chip);
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unsigned long flags;
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spin_lock_irqsave(&p->lock, flags);
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gpio_rcar_modify_bit(p, OUTDT, offset, value);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct gpio_rcar_priv *p = gpiochip_get_data(chip);
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unsigned long flags;
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u32 val, bankmask;
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bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
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if (chip->valid_mask)
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bankmask &= chip->valid_mask[0];
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if (!bankmask)
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return;
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spin_lock_irqsave(&p->lock, flags);
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val = gpio_rcar_read(p, OUTDT);
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val &= ~bankmask;
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val |= (bankmask & bits[0]);
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gpio_rcar_write(p, OUTDT, val);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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/* write GPIO value to output before selecting output mode of pin */
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gpio_rcar_set(chip, offset, value);
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gpio_rcar_config_general_input_output_mode(chip, offset, true);
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return 0;
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}
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struct gpio_rcar_info {
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bool has_both_edge_trigger;
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};
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static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
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.has_both_edge_trigger = false,
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};
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static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
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.has_both_edge_trigger = true,
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};
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static const struct of_device_id gpio_rcar_of_table[] = {
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{
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.compatible = "renesas,gpio-r8a7743",
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/* RZ/G1 GPIO is identical to R-Car Gen2. */
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7790",
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7791",
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7792",
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7793",
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7794",
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7795",
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/* Gen3 GPIO is identical to Gen2. */
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-r8a7796",
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/* Gen3 GPIO is identical to Gen2. */
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,rcar-gen1-gpio",
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.data = &gpio_rcar_info_gen1,
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}, {
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.compatible = "renesas,rcar-gen2-gpio",
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,rcar-gen3-gpio",
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/* Gen3 GPIO is identical to Gen2. */
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.data = &gpio_rcar_info_gen2,
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}, {
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.compatible = "renesas,gpio-rcar",
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.data = &gpio_rcar_info_gen1,
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}, {
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/* Terminator */
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},
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};
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MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
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static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
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{
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struct device_node *np = p->pdev->dev.of_node;
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const struct gpio_rcar_info *info;
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struct of_phandle_args args;
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int ret;
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info = of_device_get_match_data(&p->pdev->dev);
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ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
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*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
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p->has_both_edge_trigger = info->has_both_edge_trigger;
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if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
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dev_warn(&p->pdev->dev,
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"Invalid number of gpio lines %u, using %u\n", *npins,
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RCAR_MAX_GPIO_PER_BANK);
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*npins = RCAR_MAX_GPIO_PER_BANK;
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}
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return 0;
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}
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static int gpio_rcar_probe(struct platform_device *pdev)
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{
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struct gpio_rcar_priv *p;
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struct resource *io, *irq;
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struct gpio_chip *gpio_chip;
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struct irq_chip *irq_chip;
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struct device *dev = &pdev->dev;
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const char *name = dev_name(dev);
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unsigned int npins;
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int ret;
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p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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p->pdev = pdev;
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spin_lock_init(&p->lock);
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/* Get device configuration from DT node */
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ret = gpio_rcar_parse_dt(p, &npins);
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if (ret < 0)
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return ret;
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platform_set_drvdata(pdev, p);
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pm_runtime_enable(dev);
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!irq) {
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dev_err(dev, "missing IRQ\n");
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ret = -EINVAL;
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goto err0;
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}
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io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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p->base = devm_ioremap_resource(dev, io);
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if (IS_ERR(p->base)) {
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ret = PTR_ERR(p->base);
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goto err0;
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}
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gpio_chip = &p->gpio_chip;
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gpio_chip->request = gpio_rcar_request;
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gpio_chip->free = gpio_rcar_free;
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gpio_chip->get_direction = gpio_rcar_get_direction;
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gpio_chip->direction_input = gpio_rcar_direction_input;
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gpio_chip->get = gpio_rcar_get;
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gpio_chip->direction_output = gpio_rcar_direction_output;
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gpio_chip->set = gpio_rcar_set;
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gpio_chip->set_multiple = gpio_rcar_set_multiple;
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gpio_chip->label = name;
|
|
gpio_chip->parent = dev;
|
|
gpio_chip->owner = THIS_MODULE;
|
|
gpio_chip->base = -1;
|
|
gpio_chip->ngpio = npins;
|
|
|
|
irq_chip = &p->irq_chip;
|
|
irq_chip->name = name;
|
|
irq_chip->parent_device = dev;
|
|
irq_chip->irq_mask = gpio_rcar_irq_disable;
|
|
irq_chip->irq_unmask = gpio_rcar_irq_enable;
|
|
irq_chip->irq_set_type = gpio_rcar_irq_set_type;
|
|
irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
|
|
irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
|
|
|
|
ret = gpiochip_add_data(gpio_chip, p);
|
|
if (ret) {
|
|
dev_err(dev, "failed to add GPIO controller\n");
|
|
goto err0;
|
|
}
|
|
|
|
ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
|
|
IRQ_TYPE_NONE);
|
|
if (ret) {
|
|
dev_err(dev, "cannot add irqchip\n");
|
|
goto err1;
|
|
}
|
|
|
|
p->irq_parent = irq->start;
|
|
if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
|
|
IRQF_SHARED, name, p)) {
|
|
dev_err(dev, "failed to request IRQ\n");
|
|
ret = -ENOENT;
|
|
goto err1;
|
|
}
|
|
|
|
dev_info(dev, "driving %d GPIOs\n", npins);
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
gpiochip_remove(gpio_chip);
|
|
err0:
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int gpio_rcar_remove(struct platform_device *pdev)
|
|
{
|
|
struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
|
|
|
|
gpiochip_remove(&p->gpio_chip);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int gpio_rcar_suspend(struct device *dev)
|
|
{
|
|
struct gpio_rcar_priv *p = dev_get_drvdata(dev);
|
|
|
|
p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
|
|
p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
|
|
p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
|
|
p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
|
|
p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
|
|
p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
|
|
if (p->has_both_edge_trigger)
|
|
p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
|
|
|
|
if (atomic_read(&p->wakeup_path))
|
|
device_set_wakeup_path(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpio_rcar_resume(struct device *dev)
|
|
{
|
|
struct gpio_rcar_priv *p = dev_get_drvdata(dev);
|
|
unsigned int offset;
|
|
u32 mask;
|
|
|
|
for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
|
|
if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
|
|
continue;
|
|
|
|
mask = BIT(offset);
|
|
/* I/O pin */
|
|
if (!(p->bank_info.iointsel & mask)) {
|
|
if (p->bank_info.inoutsel & mask)
|
|
gpio_rcar_direction_output(
|
|
&p->gpio_chip, offset,
|
|
!!(p->bank_info.outdt & mask));
|
|
else
|
|
gpio_rcar_direction_input(&p->gpio_chip,
|
|
offset);
|
|
} else {
|
|
/* Interrupt pin */
|
|
gpio_rcar_config_interrupt_input_mode(
|
|
p,
|
|
offset,
|
|
!(p->bank_info.posneg & mask),
|
|
!(p->bank_info.edglevel & mask),
|
|
!!(p->bank_info.bothedge & mask));
|
|
|
|
if (p->bank_info.intmsk & mask)
|
|
gpio_rcar_write(p, MSKCLR, mask);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP*/
|
|
|
|
static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
|
|
|
|
static struct platform_driver gpio_rcar_device_driver = {
|
|
.probe = gpio_rcar_probe,
|
|
.remove = gpio_rcar_remove,
|
|
.driver = {
|
|
.name = "gpio_rcar",
|
|
.pm = &gpio_rcar_pm_ops,
|
|
.of_match_table = of_match_ptr(gpio_rcar_of_table),
|
|
}
|
|
};
|
|
|
|
module_platform_driver(gpio_rcar_device_driver);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
|
|
MODULE_LICENSE("GPL v2");
|