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![Sibi Sankar](/assets/img/avatar_default.png)
Add reset controller driver for Qualcomm SDM845 SoC to control reset signals provided by AOSS for Modem, Venus ADSP, GPU, Camera, Wireless, Display subsystem Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 The Linux Foundation. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of_device.h>
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#include <dt-bindings/reset/qcom,sdm845-aoss.h>
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struct qcom_aoss_reset_map {
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unsigned int reg;
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};
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struct qcom_aoss_desc {
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const struct qcom_aoss_reset_map *resets;
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size_t num_resets;
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};
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struct qcom_aoss_reset_data {
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struct reset_controller_dev rcdev;
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void __iomem *base;
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const struct qcom_aoss_desc *desc;
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};
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static const struct qcom_aoss_reset_map sdm845_aoss_resets[] = {
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[AOSS_CC_MSS_RESTART] = {0x10000},
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[AOSS_CC_CAMSS_RESTART] = {0x11000},
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[AOSS_CC_VENUS_RESTART] = {0x12000},
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[AOSS_CC_GPU_RESTART] = {0x13000},
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[AOSS_CC_DISPSS_RESTART] = {0x14000},
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[AOSS_CC_WCSS_RESTART] = {0x20000},
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[AOSS_CC_LPASS_RESTART] = {0x30000},
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};
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static const struct qcom_aoss_desc sdm845_aoss_desc = {
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.resets = sdm845_aoss_resets,
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.num_resets = ARRAY_SIZE(sdm845_aoss_resets),
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};
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static inline struct qcom_aoss_reset_data *to_qcom_aoss_reset_data(
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struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct qcom_aoss_reset_data, rcdev);
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}
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static int qcom_aoss_control_assert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
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const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
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writel(1, data->base + map->reg);
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/* Wait 6 32kHz sleep cycles for reset */
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usleep_range(200, 300);
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return 0;
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}
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static int qcom_aoss_control_deassert(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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struct qcom_aoss_reset_data *data = to_qcom_aoss_reset_data(rcdev);
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const struct qcom_aoss_reset_map *map = &data->desc->resets[idx];
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writel(0, data->base + map->reg);
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/* Wait 6 32kHz sleep cycles for reset */
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usleep_range(200, 300);
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return 0;
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}
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static int qcom_aoss_control_reset(struct reset_controller_dev *rcdev,
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unsigned long idx)
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{
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qcom_aoss_control_assert(rcdev, idx);
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return qcom_aoss_control_deassert(rcdev, idx);
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}
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static const struct reset_control_ops qcom_aoss_reset_ops = {
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.reset = qcom_aoss_control_reset,
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.assert = qcom_aoss_control_assert,
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.deassert = qcom_aoss_control_deassert,
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};
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static int qcom_aoss_reset_probe(struct platform_device *pdev)
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{
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struct qcom_aoss_reset_data *data;
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struct device *dev = &pdev->dev;
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const struct qcom_aoss_desc *desc;
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struct resource *res;
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desc = of_device_get_match_data(dev);
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if (!desc)
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return -EINVAL;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->desc = desc;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(data->base))
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return PTR_ERR(data->base);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.ops = &qcom_aoss_reset_ops;
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data->rcdev.nr_resets = desc->num_resets;
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data->rcdev.of_node = dev->of_node;
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return devm_reset_controller_register(dev, &data->rcdev);
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}
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static const struct of_device_id qcom_aoss_reset_of_match[] = {
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{ .compatible = "qcom,sdm845-aoss-cc", .data = &sdm845_aoss_desc },
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{}
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};
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static struct platform_driver qcom_aoss_reset_driver = {
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.probe = qcom_aoss_reset_probe,
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.driver = {
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.name = "qcom_aoss_reset",
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.of_match_table = qcom_aoss_reset_of_match,
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},
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};
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builtin_platform_driver(qcom_aoss_reset_driver);
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MODULE_DESCRIPTION("Qualcomm AOSS Reset Driver");
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MODULE_LICENSE("GPL v2");
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