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![Alex Dai](/assets/img/avatar_default.png)
Previously GuC uses ring id as engine id because of same definition.
But this is not true since this commit:
commit de1add3605
Author: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Date: Fri Jan 15 15:12:50 2016 +0000
drm/i915: Decouple execbuf uAPI from internal implementation
Added GuC engine id into GuC interface to decouple it from ring id used
by driver.
v2: Keep ring name print out in debugfs; using for_each_ring() where
possible to keep driver consistent. (Chris W.)
Signed-off-by: Alex Dai <yu.dai@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453579094-29860-1-git-send-email-yu.dai@intel.com
1029 lines
28 KiB
C
1029 lines
28 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/circ_buf.h>
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#include "i915_drv.h"
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#include "intel_guc.h"
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/**
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* DOC: GuC-based command submission
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*
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* i915_guc_client:
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* We use the term client to avoid confusion with contexts. A i915_guc_client is
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* equivalent to GuC object guc_context_desc. This context descriptor is
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* allocated from a pool of 1024 entries. Kernel driver will allocate doorbell
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* and workqueue for it. Also the process descriptor (guc_process_desc), which
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* is mapped to client space. So the client can write Work Item then ring the
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* doorbell.
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*
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* To simplify the implementation, we allocate one gem object that contains all
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* pages for doorbell, process descriptor and workqueue.
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*
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* The Scratch registers:
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* There are 16 MMIO-based registers start from 0xC180. The kernel driver writes
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* a value to the action register (SOFT_SCRATCH_0) along with any data. It then
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* triggers an interrupt on the GuC via another register write (0xC4C8).
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* Firmware writes a success/fail code back to the action register after
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* processes the request. The kernel driver polls waiting for this update and
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* then proceeds.
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* See host2guc_action()
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*
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* Doorbells:
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* Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW)
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* mapped into process space.
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*
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* Work Items:
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* There are several types of work items that the host may place into a
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* workqueue, each with its own requirements and limitations. Currently only
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* WQ_TYPE_INORDER is needed to support legacy submission via GuC, which
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* represents in-order queue. The kernel driver packs ring tail pointer and an
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* ELSP context descriptor dword into Work Item.
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* See guc_add_workqueue_item()
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*
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*/
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/*
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* Read GuC command/status register (SOFT_SCRATCH_0)
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* Return true if it contains a response rather than a command
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*/
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static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
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u32 *status)
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{
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u32 val = I915_READ(SOFT_SCRATCH(0));
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*status = val;
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return GUC2HOST_IS_RESPONSE(val);
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}
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static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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u32 status;
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int i;
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int ret;
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if (WARN_ON(len < 1 || len > 15))
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return -EINVAL;
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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dev_priv->guc.action_count += 1;
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dev_priv->guc.action_cmd = data[0];
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for (i = 0; i < len; i++)
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I915_WRITE(SOFT_SCRATCH(i), data[i]);
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POSTING_READ(SOFT_SCRATCH(i - 1));
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I915_WRITE(HOST2GUC_INTERRUPT, HOST2GUC_TRIGGER);
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/* No HOST2GUC command should take longer than 10ms */
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ret = wait_for_atomic(host2guc_action_response(dev_priv, &status), 10);
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if (status != GUC2HOST_STATUS_SUCCESS) {
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/*
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* Either the GuC explicitly returned an error (which
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* we convert to -EIO here) or no response at all was
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* received within the timeout limit (-ETIMEDOUT)
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*/
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if (ret != -ETIMEDOUT)
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ret = -EIO;
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DRM_ERROR("GUC: host2guc action 0x%X failed. ret=%d "
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"status=0x%08X response=0x%08X\n",
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data[0], ret, status,
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I915_READ(SOFT_SCRATCH(15)));
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dev_priv->guc.action_fail += 1;
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dev_priv->guc.action_err = ret;
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}
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dev_priv->guc.action_status = status;
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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return ret;
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}
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/*
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* Tell the GuC to allocate or deallocate a specific doorbell
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*/
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static int host2guc_allocate_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL;
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data[1] = client->ctx_index;
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return host2guc_action(guc, data, 2);
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}
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static int host2guc_release_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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u32 data[2];
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data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL;
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data[1] = client->ctx_index;
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return host2guc_action(guc, data, 2);
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}
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static int host2guc_sample_forcewake(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct drm_device *dev = dev_priv->dev;
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u32 data[2];
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data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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if (!intel_enable_rc6(dev) ||
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NEEDS_WaRsDisableCoarsePowerGating(dev))
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data[1] = 0;
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else
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/* bit 0 and 1 are for Render and Media domain separately */
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data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
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return host2guc_action(guc, data, ARRAY_SIZE(data));
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}
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/*
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* Initialise, update, or clear doorbell data shared with the GuC
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*
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* These functions modify shared data and so need access to the mapped
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* client object which contains the page being used for the doorbell
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*/
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static void guc_init_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_doorbell_info *doorbell;
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void *base;
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base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
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doorbell = base + client->doorbell_offset;
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doorbell->db_status = 1;
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doorbell->cookie = 0;
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kunmap_atomic(base);
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}
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static int guc_ring_doorbell(struct i915_guc_client *gc)
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{
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struct guc_process_desc *desc;
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union guc_doorbell_qw db_cmp, db_exc, db_ret;
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union guc_doorbell_qw *db;
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void *base;
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int attempt = 2, ret = -EAGAIN;
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base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
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desc = base + gc->proc_desc_offset;
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/* Update the tail so it is visible to GuC */
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desc->tail = gc->wq_tail;
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/* current cookie */
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db_cmp.db_status = GUC_DOORBELL_ENABLED;
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db_cmp.cookie = gc->cookie;
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/* cookie to be updated */
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db_exc.db_status = GUC_DOORBELL_ENABLED;
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db_exc.cookie = gc->cookie + 1;
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if (db_exc.cookie == 0)
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db_exc.cookie = 1;
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/* pointer of current doorbell cacheline */
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db = base + gc->doorbell_offset;
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while (attempt--) {
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/* lets ring the doorbell */
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db_ret.value_qw = atomic64_cmpxchg((atomic64_t *)db,
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db_cmp.value_qw, db_exc.value_qw);
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/* if the exchange was successfully executed */
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if (db_ret.value_qw == db_cmp.value_qw) {
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/* db was successfully rung */
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gc->cookie = db_exc.cookie;
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ret = 0;
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break;
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}
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/* XXX: doorbell was lost and need to acquire it again */
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if (db_ret.db_status == GUC_DOORBELL_DISABLED)
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break;
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DRM_ERROR("Cookie mismatch. Expected %d, returned %d\n",
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db_cmp.cookie, db_ret.cookie);
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/* update the cookie to newly read cookie from GuC */
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db_cmp.cookie = db_ret.cookie;
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db_exc.cookie = db_ret.cookie + 1;
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if (db_exc.cookie == 0)
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db_exc.cookie = 1;
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}
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/* Finally, update the cached copy of the GuC's WQ head */
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gc->wq_head = desc->head;
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kunmap_atomic(base);
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return ret;
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}
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static void guc_disable_doorbell(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct guc_doorbell_info *doorbell;
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void *base;
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i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id);
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int value;
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base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
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doorbell = base + client->doorbell_offset;
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doorbell->db_status = 0;
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kunmap_atomic(base);
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I915_WRITE(drbreg, I915_READ(drbreg) & ~GEN8_DRB_VALID);
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value = I915_READ(drbreg);
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WARN_ON((value & GEN8_DRB_VALID) != 0);
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I915_WRITE(GEN8_DRBREGU(client->doorbell_id), 0);
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I915_WRITE(drbreg, 0);
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/* XXX: wait for any interrupts */
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/* XXX: wait for workqueue to drain */
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}
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/*
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* Select, assign and relase doorbell cachelines
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*
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* These functions track which doorbell cachelines are in use.
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* The data they manipulate is protected by the host2guc lock.
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*/
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static uint32_t select_doorbell_cacheline(struct intel_guc *guc)
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{
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const uint32_t cacheline_size = cache_line_size();
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uint32_t offset;
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/* Doorbell uses a single cache line within a page */
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offset = offset_in_page(guc->db_cacheline);
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/* Moving to next cache line to reduce contention */
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guc->db_cacheline += cacheline_size;
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DRM_DEBUG_DRIVER("selected doorbell cacheline 0x%x, next 0x%x, linesize %u\n",
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offset, guc->db_cacheline, cacheline_size);
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return offset;
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}
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static uint16_t assign_doorbell(struct intel_guc *guc, uint32_t priority)
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{
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/*
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* The bitmap is split into two halves; the first half is used for
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* normal priority contexts, the second half for high-priority ones.
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* Note that logically higher priorities are numerically less than
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* normal ones, so the test below means "is it high-priority?"
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*/
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const bool hi_pri = (priority <= GUC_CTX_PRIORITY_HIGH);
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const uint16_t half = GUC_MAX_DOORBELLS / 2;
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const uint16_t start = hi_pri ? half : 0;
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const uint16_t end = start + half;
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uint16_t id;
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id = find_next_zero_bit(guc->doorbell_bitmap, end, start);
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if (id == end)
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id = GUC_INVALID_DOORBELL_ID;
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else
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bitmap_set(guc->doorbell_bitmap, id, 1);
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DRM_DEBUG_DRIVER("assigned %s priority doorbell id 0x%x\n",
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hi_pri ? "high" : "normal", id);
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return id;
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}
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static void release_doorbell(struct intel_guc *guc, uint16_t id)
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{
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bitmap_clear(guc->doorbell_bitmap, id, 1);
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}
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/*
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* Initialise the process descriptor shared with the GuC firmware.
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*/
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static void guc_init_proc_desc(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_process_desc *desc;
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void *base;
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base = kmap_atomic(i915_gem_object_get_page(client->client_obj, 0));
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desc = base + client->proc_desc_offset;
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memset(desc, 0, sizeof(*desc));
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/*
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* XXX: pDoorbell and WQVBaseAddress are pointers in process address
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* space for ring3 clients (set them as in mmap_ioctl) or kernel
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* space for kernel clients (map on demand instead? May make debug
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* easier to have it mapped).
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*/
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desc->wq_base_addr = 0;
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desc->db_base_addr = 0;
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desc->context_id = client->ctx_index;
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desc->wq_size_bytes = client->wq_size;
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desc->wq_status = WQ_STATUS_ACTIVE;
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desc->priority = client->priority;
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kunmap_atomic(base);
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}
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/*
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* Initialise/clear the context descriptor shared with the GuC firmware.
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*
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* This descriptor tells the GuC where (in GGTT space) to find the important
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* data structures relating to this client (doorbell, process descriptor,
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* write queue, etc).
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*/
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static void guc_init_ctx_desc(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct drm_i915_private *dev_priv = guc_to_i915(guc);
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struct intel_engine_cs *ring;
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struct intel_context *ctx = client->owner;
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struct guc_context_desc desc;
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struct sg_table *sg;
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int i;
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memset(&desc, 0, sizeof(desc));
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desc.attribute = GUC_CTX_DESC_ATTR_ACTIVE | GUC_CTX_DESC_ATTR_KERNEL;
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desc.context_id = client->ctx_index;
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desc.priority = client->priority;
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desc.db_id = client->doorbell_id;
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for_each_ring(ring, dev_priv, i) {
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struct guc_execlist_context *lrc = &desc.lrc[ring->guc_id];
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struct drm_i915_gem_object *obj;
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uint64_t ctx_desc;
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/* TODO: We have a design issue to be solved here. Only when we
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* receive the first batch, we know which engine is used by the
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* user. But here GuC expects the lrc and ring to be pinned. It
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* is not an issue for default context, which is the only one
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* for now who owns a GuC client. But for future owner of GuC
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* client, need to make sure lrc is pinned prior to enter here.
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*/
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obj = ctx->engine[i].state;
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if (!obj)
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break; /* XXX: continue? */
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ctx_desc = intel_lr_context_descriptor(ctx, ring);
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lrc->context_desc = (u32)ctx_desc;
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/* The state page is after PPHWSP */
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lrc->ring_lcra = i915_gem_obj_ggtt_offset(obj) +
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LRC_STATE_PN * PAGE_SIZE;
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lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) |
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(ring->guc_id << GUC_ELC_ENGINE_OFFSET);
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obj = ctx->engine[i].ringbuf->obj;
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lrc->ring_begin = i915_gem_obj_ggtt_offset(obj);
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lrc->ring_end = lrc->ring_begin + obj->base.size - 1;
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lrc->ring_next_free_location = lrc->ring_begin;
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lrc->ring_current_tail_pointer_value = 0;
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desc.engines_used |= (1 << ring->guc_id);
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}
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WARN_ON(desc.engines_used == 0);
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/*
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* The CPU address is only needed at certain points, so kmap_atomic on
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* demand instead of storing it in the ctx descriptor.
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* XXX: May make debug easier to have it mapped
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*/
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desc.db_trigger_cpu = 0;
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desc.db_trigger_uk = client->doorbell_offset +
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i915_gem_obj_ggtt_offset(client->client_obj);
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desc.db_trigger_phy = client->doorbell_offset +
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sg_dma_address(client->client_obj->pages->sgl);
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desc.process_desc = client->proc_desc_offset +
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i915_gem_obj_ggtt_offset(client->client_obj);
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desc.wq_addr = client->wq_offset +
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i915_gem_obj_ggtt_offset(client->client_obj);
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desc.wq_size = client->wq_size;
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/*
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* XXX: Take LRCs from an existing intel_context if this is not an
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* IsKMDCreatedContext client
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*/
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desc.desc_private = (uintptr_t)client;
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/* Pool context is pinned already */
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sg = guc->ctx_pool_obj->pages;
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sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
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sizeof(desc) * client->ctx_index);
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}
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static void guc_fini_ctx_desc(struct intel_guc *guc,
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struct i915_guc_client *client)
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{
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struct guc_context_desc desc;
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struct sg_table *sg;
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memset(&desc, 0, sizeof(desc));
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|
|
sg = guc->ctx_pool_obj->pages;
|
|
sg_pcopy_from_buffer(sg->sgl, sg->nents, &desc, sizeof(desc),
|
|
sizeof(desc) * client->ctx_index);
|
|
}
|
|
|
|
int i915_guc_wq_check_space(struct i915_guc_client *gc)
|
|
{
|
|
struct guc_process_desc *desc;
|
|
void *base;
|
|
u32 size = sizeof(struct guc_wq_item);
|
|
int ret = -ETIMEDOUT, timeout_counter = 200;
|
|
|
|
if (!gc)
|
|
return 0;
|
|
|
|
/* Quickly return if wq space is available since last time we cache the
|
|
* head position. */
|
|
if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size)
|
|
return 0;
|
|
|
|
base = kmap_atomic(i915_gem_object_get_page(gc->client_obj, 0));
|
|
desc = base + gc->proc_desc_offset;
|
|
|
|
while (timeout_counter-- > 0) {
|
|
gc->wq_head = desc->head;
|
|
|
|
if (CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size) >= size) {
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
if (timeout_counter)
|
|
usleep_range(1000, 2000);
|
|
};
|
|
|
|
kunmap_atomic(base);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int guc_add_workqueue_item(struct i915_guc_client *gc,
|
|
struct drm_i915_gem_request *rq)
|
|
{
|
|
struct guc_wq_item *wqi;
|
|
void *base;
|
|
u32 tail, wq_len, wq_off, space;
|
|
|
|
space = CIRC_SPACE(gc->wq_tail, gc->wq_head, gc->wq_size);
|
|
if (WARN_ON(space < sizeof(struct guc_wq_item)))
|
|
return -ENOSPC; /* shouldn't happen */
|
|
|
|
/* postincrement WQ tail for next time */
|
|
wq_off = gc->wq_tail;
|
|
gc->wq_tail += sizeof(struct guc_wq_item);
|
|
gc->wq_tail &= gc->wq_size - 1;
|
|
|
|
/* For now workqueue item is 4 DWs; workqueue buffer is 2 pages. So we
|
|
* should not have the case where structure wqi is across page, neither
|
|
* wrapped to the beginning. This simplifies the implementation below.
|
|
*
|
|
* XXX: if not the case, we need save data to a temp wqi and copy it to
|
|
* workqueue buffer dw by dw.
|
|
*/
|
|
WARN_ON(sizeof(struct guc_wq_item) != 16);
|
|
WARN_ON(wq_off & 3);
|
|
|
|
/* wq starts from the page after doorbell / process_desc */
|
|
base = kmap_atomic(i915_gem_object_get_page(gc->client_obj,
|
|
(wq_off + GUC_DB_SIZE) >> PAGE_SHIFT));
|
|
wq_off &= PAGE_SIZE - 1;
|
|
wqi = (struct guc_wq_item *)((char *)base + wq_off);
|
|
|
|
/* len does not include the header */
|
|
wq_len = sizeof(struct guc_wq_item) / sizeof(u32) - 1;
|
|
wqi->header = WQ_TYPE_INORDER |
|
|
(wq_len << WQ_LEN_SHIFT) |
|
|
(rq->ring->guc_id << WQ_TARGET_SHIFT) |
|
|
WQ_NO_WCFLUSH_WAIT;
|
|
|
|
/* The GuC wants only the low-order word of the context descriptor */
|
|
wqi->context_desc = (u32)intel_lr_context_descriptor(rq->ctx, rq->ring);
|
|
|
|
/* The GuC firmware wants the tail index in QWords, not bytes */
|
|
tail = rq->ringbuf->tail >> 3;
|
|
wqi->ring_tail = tail << WQ_RING_TAIL_SHIFT;
|
|
wqi->fence_id = 0; /*XXX: what fence to be here */
|
|
|
|
kunmap_atomic(base);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* i915_guc_submit() - Submit commands through GuC
|
|
* @client: the guc client where commands will go through
|
|
* @rq: request associated with the commands
|
|
*
|
|
* Return: 0 if succeed
|
|
*/
|
|
int i915_guc_submit(struct i915_guc_client *client,
|
|
struct drm_i915_gem_request *rq)
|
|
{
|
|
struct intel_guc *guc = client->guc;
|
|
unsigned int engine_id = rq->ring->guc_id;
|
|
int q_ret, b_ret;
|
|
|
|
q_ret = guc_add_workqueue_item(client, rq);
|
|
if (q_ret == 0)
|
|
b_ret = guc_ring_doorbell(client);
|
|
|
|
client->submissions[engine_id] += 1;
|
|
if (q_ret) {
|
|
client->q_fail += 1;
|
|
client->retcode = q_ret;
|
|
} else if (b_ret) {
|
|
client->b_fail += 1;
|
|
client->retcode = q_ret = b_ret;
|
|
} else {
|
|
client->retcode = 0;
|
|
}
|
|
guc->submissions[engine_id] += 1;
|
|
guc->last_seqno[engine_id] = rq->seqno;
|
|
|
|
return q_ret;
|
|
}
|
|
|
|
/*
|
|
* Everything below here is concerned with setup & teardown, and is
|
|
* therefore not part of the somewhat time-critical batch-submission
|
|
* path of i915_guc_submit() above.
|
|
*/
|
|
|
|
/**
|
|
* gem_allocate_guc_obj() - Allocate gem object for GuC usage
|
|
* @dev: drm device
|
|
* @size: size of object
|
|
*
|
|
* This is a wrapper to create a gem obj. In order to use it inside GuC, the
|
|
* object needs to be pinned lifetime. Also we must pin it to gtt space other
|
|
* than [0, GUC_WOPCM_TOP) because this range is reserved inside GuC.
|
|
*
|
|
* Return: A drm_i915_gem_object if successful, otherwise NULL.
|
|
*/
|
|
static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device *dev,
|
|
u32 size)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
obj = i915_gem_alloc_object(dev, size);
|
|
if (!obj)
|
|
return NULL;
|
|
|
|
if (i915_gem_object_get_pages(obj)) {
|
|
drm_gem_object_unreference(&obj->base);
|
|
return NULL;
|
|
}
|
|
|
|
if (i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
|
|
PIN_OFFSET_BIAS | GUC_WOPCM_TOP)) {
|
|
drm_gem_object_unreference(&obj->base);
|
|
return NULL;
|
|
}
|
|
|
|
/* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
|
|
I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
|
|
|
|
return obj;
|
|
}
|
|
|
|
/**
|
|
* gem_release_guc_obj() - Release gem object allocated for GuC usage
|
|
* @obj: gem obj to be released
|
|
*/
|
|
static void gem_release_guc_obj(struct drm_i915_gem_object *obj)
|
|
{
|
|
if (!obj)
|
|
return;
|
|
|
|
if (i915_gem_obj_is_pinned(obj))
|
|
i915_gem_object_ggtt_unpin(obj);
|
|
|
|
drm_gem_object_unreference(&obj->base);
|
|
}
|
|
|
|
static void guc_client_free(struct drm_device *dev,
|
|
struct i915_guc_client *client)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
if (!client)
|
|
return;
|
|
|
|
if (client->doorbell_id != GUC_INVALID_DOORBELL_ID) {
|
|
/*
|
|
* First disable the doorbell, then tell the GuC we've
|
|
* finished with it, finally deallocate it in our bitmap
|
|
*/
|
|
guc_disable_doorbell(guc, client);
|
|
host2guc_release_doorbell(guc, client);
|
|
release_doorbell(guc, client->doorbell_id);
|
|
}
|
|
|
|
/*
|
|
* XXX: wait for any outstanding submissions before freeing memory.
|
|
* Be sure to drop any locks
|
|
*/
|
|
|
|
gem_release_guc_obj(client->client_obj);
|
|
|
|
if (client->ctx_index != GUC_INVALID_CTX_ID) {
|
|
guc_fini_ctx_desc(guc, client);
|
|
ida_simple_remove(&guc->ctx_ids, client->ctx_index);
|
|
}
|
|
|
|
kfree(client);
|
|
}
|
|
|
|
/**
|
|
* guc_client_alloc() - Allocate an i915_guc_client
|
|
* @dev: drm device
|
|
* @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
|
|
* The kernel client to replace ExecList submission is created with
|
|
* NORMAL priority. Priority of a client for scheduler can be HIGH,
|
|
* while a preemption context can use CRITICAL.
|
|
* @ctx: the context that owns the client (we use the default render
|
|
* context)
|
|
*
|
|
* Return: An i915_guc_client object if success.
|
|
*/
|
|
static struct i915_guc_client *guc_client_alloc(struct drm_device *dev,
|
|
uint32_t priority,
|
|
struct intel_context *ctx)
|
|
{
|
|
struct i915_guc_client *client;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
client = kzalloc(sizeof(*client), GFP_KERNEL);
|
|
if (!client)
|
|
return NULL;
|
|
|
|
client->doorbell_id = GUC_INVALID_DOORBELL_ID;
|
|
client->priority = priority;
|
|
client->owner = ctx;
|
|
client->guc = guc;
|
|
|
|
client->ctx_index = (uint32_t)ida_simple_get(&guc->ctx_ids, 0,
|
|
GUC_MAX_GPU_CONTEXTS, GFP_KERNEL);
|
|
if (client->ctx_index >= GUC_MAX_GPU_CONTEXTS) {
|
|
client->ctx_index = GUC_INVALID_CTX_ID;
|
|
goto err;
|
|
}
|
|
|
|
/* The first page is doorbell/proc_desc. Two followed pages are wq. */
|
|
obj = gem_allocate_guc_obj(dev, GUC_DB_SIZE + GUC_WQ_SIZE);
|
|
if (!obj)
|
|
goto err;
|
|
|
|
client->client_obj = obj;
|
|
client->wq_offset = GUC_DB_SIZE;
|
|
client->wq_size = GUC_WQ_SIZE;
|
|
|
|
client->doorbell_offset = select_doorbell_cacheline(guc);
|
|
|
|
/*
|
|
* Since the doorbell only requires a single cacheline, we can save
|
|
* space by putting the application process descriptor in the same
|
|
* page. Use the half of the page that doesn't include the doorbell.
|
|
*/
|
|
if (client->doorbell_offset >= (GUC_DB_SIZE / 2))
|
|
client->proc_desc_offset = 0;
|
|
else
|
|
client->proc_desc_offset = (GUC_DB_SIZE / 2);
|
|
|
|
client->doorbell_id = assign_doorbell(guc, client->priority);
|
|
if (client->doorbell_id == GUC_INVALID_DOORBELL_ID)
|
|
/* XXX: evict a doorbell instead */
|
|
goto err;
|
|
|
|
guc_init_proc_desc(guc, client);
|
|
guc_init_ctx_desc(guc, client);
|
|
guc_init_doorbell(guc, client);
|
|
|
|
/* XXX: Any cache flushes needed? General domain mgmt calls? */
|
|
|
|
if (host2guc_allocate_doorbell(guc, client))
|
|
goto err;
|
|
|
|
DRM_DEBUG_DRIVER("new priority %u client %p: ctx_index %u db_id %u\n",
|
|
priority, client, client->ctx_index, client->doorbell_id);
|
|
|
|
return client;
|
|
|
|
err:
|
|
DRM_ERROR("FAILED to create priority %u GuC client!\n", priority);
|
|
|
|
guc_client_free(dev, client);
|
|
return NULL;
|
|
}
|
|
|
|
static void guc_create_log(struct intel_guc *guc)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
struct drm_i915_gem_object *obj;
|
|
unsigned long offset;
|
|
uint32_t size, flags;
|
|
|
|
if (i915.guc_log_level < GUC_LOG_VERBOSITY_MIN)
|
|
return;
|
|
|
|
if (i915.guc_log_level > GUC_LOG_VERBOSITY_MAX)
|
|
i915.guc_log_level = GUC_LOG_VERBOSITY_MAX;
|
|
|
|
/* The first page is to save log buffer state. Allocate one
|
|
* extra page for others in case for overlap */
|
|
size = (1 + GUC_LOG_DPC_PAGES + 1 +
|
|
GUC_LOG_ISR_PAGES + 1 +
|
|
GUC_LOG_CRASH_PAGES + 1) << PAGE_SHIFT;
|
|
|
|
obj = guc->log_obj;
|
|
if (!obj) {
|
|
obj = gem_allocate_guc_obj(dev_priv->dev, size);
|
|
if (!obj) {
|
|
/* logging will be off */
|
|
i915.guc_log_level = -1;
|
|
return;
|
|
}
|
|
|
|
guc->log_obj = obj;
|
|
}
|
|
|
|
/* each allocated unit is a page */
|
|
flags = GUC_LOG_VALID | GUC_LOG_NOTIFY_ON_HALF_FULL |
|
|
(GUC_LOG_DPC_PAGES << GUC_LOG_DPC_SHIFT) |
|
|
(GUC_LOG_ISR_PAGES << GUC_LOG_ISR_SHIFT) |
|
|
(GUC_LOG_CRASH_PAGES << GUC_LOG_CRASH_SHIFT);
|
|
|
|
offset = i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT; /* in pages */
|
|
guc->log_flags = (offset << GUC_LOG_BUF_ADDR_SHIFT) | flags;
|
|
}
|
|
|
|
static void init_guc_policies(struct guc_policies *policies)
|
|
{
|
|
struct guc_policy *policy;
|
|
u32 p, i;
|
|
|
|
policies->dpc_promote_time = 500000;
|
|
policies->max_num_work_items = POLICY_MAX_NUM_WI;
|
|
|
|
for (p = 0; p < GUC_CTX_PRIORITY_NUM; p++) {
|
|
for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) {
|
|
policy = &policies->policy[p][i];
|
|
|
|
policy->execution_quantum = 1000000;
|
|
policy->preemption_time = 500000;
|
|
policy->fault_time = 250000;
|
|
policy->policy_flags = 0;
|
|
}
|
|
}
|
|
|
|
policies->is_valid = 1;
|
|
}
|
|
|
|
static void guc_create_ads(struct intel_guc *guc)
|
|
{
|
|
struct drm_i915_private *dev_priv = guc_to_i915(guc);
|
|
struct drm_i915_gem_object *obj;
|
|
struct guc_ads *ads;
|
|
struct guc_policies *policies;
|
|
struct guc_mmio_reg_state *reg_state;
|
|
struct intel_engine_cs *ring;
|
|
struct page *page;
|
|
u32 size, i;
|
|
|
|
/* The ads obj includes the struct itself and buffers passed to GuC */
|
|
size = sizeof(struct guc_ads) + sizeof(struct guc_policies) +
|
|
sizeof(struct guc_mmio_reg_state) +
|
|
GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;
|
|
|
|
obj = guc->ads_obj;
|
|
if (!obj) {
|
|
obj = gem_allocate_guc_obj(dev_priv->dev, PAGE_ALIGN(size));
|
|
if (!obj)
|
|
return;
|
|
|
|
guc->ads_obj = obj;
|
|
}
|
|
|
|
page = i915_gem_object_get_page(obj, 0);
|
|
ads = kmap(page);
|
|
|
|
/*
|
|
* The GuC requires a "Golden Context" when it reinitialises
|
|
* engines after a reset. Here we use the Render ring default
|
|
* context, which must already exist and be pinned in the GGTT,
|
|
* so its address won't change after we've told the GuC where
|
|
* to find it.
|
|
*/
|
|
ring = &dev_priv->ring[RCS];
|
|
ads->golden_context_lrca = ring->status_page.gfx_addr;
|
|
|
|
for_each_ring(ring, dev_priv, i)
|
|
ads->eng_state_size[ring->guc_id] = intel_lr_context_size(ring);
|
|
|
|
/* GuC scheduling policies */
|
|
policies = (void *)ads + sizeof(struct guc_ads);
|
|
init_guc_policies(policies);
|
|
|
|
ads->scheduler_policies = i915_gem_obj_ggtt_offset(obj) +
|
|
sizeof(struct guc_ads);
|
|
|
|
/* MMIO reg state */
|
|
reg_state = (void *)policies + sizeof(struct guc_policies);
|
|
|
|
for_each_ring(ring, dev_priv, i) {
|
|
reg_state->mmio_white_list[ring->guc_id].mmio_start =
|
|
ring->mmio_base + GUC_MMIO_WHITE_LIST_START;
|
|
|
|
/* Nothing to be saved or restored for now. */
|
|
reg_state->mmio_white_list[ring->guc_id].count = 0;
|
|
}
|
|
|
|
ads->reg_state_addr = ads->scheduler_policies +
|
|
sizeof(struct guc_policies);
|
|
|
|
ads->reg_state_buffer = ads->reg_state_addr +
|
|
sizeof(struct guc_mmio_reg_state);
|
|
|
|
kunmap(page);
|
|
}
|
|
|
|
/*
|
|
* Set up the memory resources to be shared with the GuC. At this point,
|
|
* we require just one object that can be mapped through the GGTT.
|
|
*/
|
|
int i915_guc_submission_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
const size_t ctxsize = sizeof(struct guc_context_desc);
|
|
const size_t poolsize = GUC_MAX_GPU_CONTEXTS * ctxsize;
|
|
const size_t gemsize = round_up(poolsize, PAGE_SIZE);
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
if (!i915.enable_guc_submission)
|
|
return 0; /* not enabled */
|
|
|
|
if (guc->ctx_pool_obj)
|
|
return 0; /* already allocated */
|
|
|
|
guc->ctx_pool_obj = gem_allocate_guc_obj(dev_priv->dev, gemsize);
|
|
if (!guc->ctx_pool_obj)
|
|
return -ENOMEM;
|
|
|
|
ida_init(&guc->ctx_ids);
|
|
|
|
guc_create_log(guc);
|
|
|
|
guc_create_ads(guc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_guc_submission_enable(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct intel_context *ctx = dev_priv->kernel_context;
|
|
struct i915_guc_client *client;
|
|
|
|
/* client for execbuf submission */
|
|
client = guc_client_alloc(dev, GUC_CTX_PRIORITY_KMD_NORMAL, ctx);
|
|
if (!client) {
|
|
DRM_ERROR("Failed to create execbuf guc_client\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
guc->execbuf_client = client;
|
|
|
|
host2guc_sample_forcewake(guc, client);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void i915_guc_submission_disable(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
guc_client_free(dev, guc->execbuf_client);
|
|
guc->execbuf_client = NULL;
|
|
}
|
|
|
|
void i915_guc_submission_fini(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
|
|
gem_release_guc_obj(dev_priv->guc.ads_obj);
|
|
guc->ads_obj = NULL;
|
|
|
|
gem_release_guc_obj(dev_priv->guc.log_obj);
|
|
guc->log_obj = NULL;
|
|
|
|
if (guc->ctx_pool_obj)
|
|
ida_destroy(&guc->ctx_ids);
|
|
gem_release_guc_obj(guc->ctx_pool_obj);
|
|
guc->ctx_pool_obj = NULL;
|
|
}
|
|
|
|
/**
|
|
* intel_guc_suspend() - notify GuC entering suspend state
|
|
* @dev: drm device
|
|
*/
|
|
int intel_guc_suspend(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct intel_context *ctx;
|
|
u32 data[3];
|
|
|
|
if (!i915.enable_guc_submission)
|
|
return 0;
|
|
|
|
ctx = dev_priv->kernel_context;
|
|
|
|
data[0] = HOST2GUC_ACTION_ENTER_S_STATE;
|
|
/* any value greater than GUC_POWER_D0 */
|
|
data[1] = GUC_POWER_D1;
|
|
/* first page is shared data with GuC */
|
|
data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
|
|
|
|
return host2guc_action(guc, data, ARRAY_SIZE(data));
|
|
}
|
|
|
|
|
|
/**
|
|
* intel_guc_resume() - notify GuC resuming from suspend state
|
|
* @dev: drm device
|
|
*/
|
|
int intel_guc_resume(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_guc *guc = &dev_priv->guc;
|
|
struct intel_context *ctx;
|
|
u32 data[3];
|
|
|
|
if (!i915.enable_guc_submission)
|
|
return 0;
|
|
|
|
ctx = dev_priv->kernel_context;
|
|
|
|
data[0] = HOST2GUC_ACTION_EXIT_S_STATE;
|
|
data[1] = GUC_POWER_D0;
|
|
/* first page is shared data with GuC */
|
|
data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state);
|
|
|
|
return host2guc_action(guc, data, ARRAY_SIZE(data));
|
|
}
|