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![Ville Syrjälä](/assets/img/avatar_default.png)
There's no need for __raw_i915_read8() & co. to be macros, so make them inline functions. To avoid typo mistakes generate the inline functions using preprocessor templates. We have a few users of the raw register acces functions outside intel_uncore.c, so let's also move the functions into intel_drv.h. While doing that switch I915_READ_FW() & co. to use the __raw_i915_read() functions, and use the _FW macros everywhere outside intel_uncore.c where we want to read registers without grabbing forcewake and whatnot. The only exception is i915_check_vgpu() which itself gets called from intel_uncore.c, so using the __raw_i915_read stuff there seems appropriate. v2: Squash in the intel_uncore.c->i915_drv.h move Convert I915_READ_FW() to use __raw_i915_read(), and use I915_READ_FW() outside of intel_uncore.c (Chris) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1445517300-28173-2-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
264 lines
9.1 KiB
C
264 lines
9.1 KiB
C
/*
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* Copyright(c) 2011-2015 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "intel_drv.h"
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#include "i915_vgpu.h"
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/**
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* DOC: Intel GVT-g guest support
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*
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* Intel GVT-g is a graphics virtualization technology which shares the
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* GPU among multiple virtual machines on a time-sharing basis. Each
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* virtual machine is presented a virtual GPU (vGPU), which has equivalent
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* features as the underlying physical GPU (pGPU), so i915 driver can run
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* seamlessly in a virtual machine. This file provides vGPU specific
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* optimizations when running in a virtual machine, to reduce the complexity
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* of vGPU emulation and to improve the overall performance.
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*
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* A primary function introduced here is so-called "address space ballooning"
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* technique. Intel GVT-g partitions global graphics memory among multiple VMs,
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* so each VM can directly access a portion of the memory without hypervisor's
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* intervention, e.g. filling textures or queuing commands. However with the
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* partitioning an unmodified i915 driver would assume a smaller graphics
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* memory starting from address ZERO, then requires vGPU emulation module to
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* translate the graphics address between 'guest view' and 'host view', for
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* all registers and command opcodes which contain a graphics memory address.
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* To reduce the complexity, Intel GVT-g introduces "address space ballooning",
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* by telling the exact partitioning knowledge to each guest i915 driver, which
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* then reserves and prevents non-allocated portions from allocation. Thus vGPU
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* emulation module only needs to scan and validate graphics addresses without
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* complexity of address translation.
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*
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*/
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/**
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* i915_check_vgpu - detect virtual GPU
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* @dev: drm device *
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*
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* This function is called at the initialization stage, to detect whether
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* running on a vGPU.
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*/
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void i915_check_vgpu(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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uint64_t magic;
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uint32_t version;
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BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
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if (!IS_HASWELL(dev))
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return;
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magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
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if (magic != VGT_MAGIC)
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return;
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version = INTEL_VGT_IF_VERSION_ENCODE(
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__raw_i915_read16(dev_priv, vgtif_reg(version_major)),
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__raw_i915_read16(dev_priv, vgtif_reg(version_minor)));
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if (version != INTEL_VGT_IF_VERSION) {
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DRM_INFO("VGT interface version mismatch!\n");
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return;
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}
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dev_priv->vgpu.active = true;
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DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
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}
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struct _balloon_info_ {
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/*
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* There are up to 2 regions per mappable/unmappable graphic
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* memory that might be ballooned. Here, index 0/1 is for mappable
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* graphic memory, 2/3 for unmappable graphic memory.
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*/
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struct drm_mm_node space[4];
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};
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static struct _balloon_info_ bl_info;
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/**
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* intel_vgt_deballoon - deballoon reserved graphics address trunks
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*
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* This function is called to deallocate the ballooned-out graphic memory, when
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* driver is unloaded or when ballooning fails.
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*/
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void intel_vgt_deballoon(void)
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{
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int i;
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DRM_DEBUG("VGT deballoon.\n");
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for (i = 0; i < 4; i++) {
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if (bl_info.space[i].allocated)
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drm_mm_remove_node(&bl_info.space[i]);
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}
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memset(&bl_info, 0, sizeof(bl_info));
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}
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static int vgt_balloon_space(struct drm_mm *mm,
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struct drm_mm_node *node,
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unsigned long start, unsigned long end)
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{
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unsigned long size = end - start;
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if (start == end)
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return -EINVAL;
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DRM_INFO("balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.\n",
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start, end, size / 1024);
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node->start = start;
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node->size = size;
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return drm_mm_reserve_node(mm, node);
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}
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/**
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* intel_vgt_balloon - balloon out reserved graphics address trunks
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* @dev: drm device
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*
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* This function is called at the initialization stage, to balloon out the
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* graphic address space allocated to other vGPUs, by marking these spaces as
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* reserved. The ballooning related knowledge(starting address and size of
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* the mappable/unmappable graphic memory) is described in the vgt_if structure
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* in a reserved mmio range.
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*
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* To give an example, the drawing below depicts one typical scenario after
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* ballooning. Here the vGPU1 has 2 pieces of graphic address spaces ballooned
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* out each for the mappable and the non-mappable part. From the vGPU1 point of
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* view, the total size is the same as the physical one, with the start address
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* of its graphic space being zero. Yet there are some portions ballooned out(
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* the shadow part, which are marked as reserved by drm allocator). From the
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* host point of view, the graphic address space is partitioned by multiple
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* vGPUs in different VMs.
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*
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* vGPU1 view Host view
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* 0 ------> +-----------+ +-----------+
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* ^ |///////////| | vGPU3 |
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* | |///////////| +-----------+
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* | |///////////| | vGPU2 |
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* | +-----------+ +-----------+
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* mappable GM | available | ==> | vGPU1 |
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* | +-----------+ +-----------+
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* | |///////////| | |
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* v |///////////| | Host |
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* +=======+===========+ +===========+
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* ^ |///////////| | vGPU3 |
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* | |///////////| +-----------+
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* | |///////////| | vGPU2 |
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* | +-----------+ +-----------+
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* unmappable GM | available | ==> | vGPU1 |
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* | +-----------+ +-----------+
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* | |///////////| | |
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* | |///////////| | Host |
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* v |///////////| | |
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* total GM size ------> +-----------+ +-----------+
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*
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* Returns:
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* zero on success, non-zero if configuration invalid or ballooning failed
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*/
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int intel_vgt_balloon(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
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unsigned long ggtt_vm_end = ggtt_vm->start + ggtt_vm->total;
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unsigned long mappable_base, mappable_size, mappable_end;
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unsigned long unmappable_base, unmappable_size, unmappable_end;
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int ret;
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mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base));
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mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size));
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unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base));
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unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size));
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mappable_end = mappable_base + mappable_size;
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unmappable_end = unmappable_base + unmappable_size;
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DRM_INFO("VGT ballooning configuration:\n");
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DRM_INFO("Mappable graphic memory: base 0x%lx size %ldKiB\n",
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mappable_base, mappable_size / 1024);
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DRM_INFO("Unmappable graphic memory: base 0x%lx size %ldKiB\n",
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unmappable_base, unmappable_size / 1024);
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if (mappable_base < ggtt_vm->start ||
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mappable_end > dev_priv->gtt.mappable_end ||
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unmappable_base < dev_priv->gtt.mappable_end ||
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unmappable_end > ggtt_vm_end) {
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DRM_ERROR("Invalid ballooning configuration!\n");
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return -EINVAL;
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}
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/* Unmappable graphic memory ballooning */
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if (unmappable_base > dev_priv->gtt.mappable_end) {
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ret = vgt_balloon_space(&ggtt_vm->mm,
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&bl_info.space[2],
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dev_priv->gtt.mappable_end,
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unmappable_base);
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if (ret)
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goto err;
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}
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/*
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* No need to partition out the last physical page,
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* because it is reserved to the guard page.
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*/
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if (unmappable_end < ggtt_vm_end - PAGE_SIZE) {
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ret = vgt_balloon_space(&ggtt_vm->mm,
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&bl_info.space[3],
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unmappable_end,
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ggtt_vm_end - PAGE_SIZE);
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if (ret)
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goto err;
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}
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/* Mappable graphic memory ballooning */
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if (mappable_base > ggtt_vm->start) {
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ret = vgt_balloon_space(&ggtt_vm->mm,
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&bl_info.space[0],
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ggtt_vm->start, mappable_base);
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if (ret)
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goto err;
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}
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if (mappable_end < dev_priv->gtt.mappable_end) {
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ret = vgt_balloon_space(&ggtt_vm->mm,
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&bl_info.space[1],
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mappable_end,
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dev_priv->gtt.mappable_end);
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if (ret)
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goto err;
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}
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DRM_INFO("VGT balloon successfully\n");
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return 0;
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err:
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DRM_ERROR("VGT balloon fail\n");
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intel_vgt_deballoon();
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return ret;
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}
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