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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-19 17:11:03 +00:00
355d8ae57b
Fixed two issues when CONFIG_RTS5139=y : - Makefile doesn't take $(CONFIG_RTS5139). It always uses obj-m and built as a loadable module. - Rename some symbols with prefix 'rts51x_' to prevent symbol name collisions with drivers/staging/rts_pstor when both are configured to be built-in objects. drivers/staging/rts5139/built-in.o: In function `xd_cleanup_work': (.text+0x1435d): multiple definition of `xd_cleanup_work' drivers/staging/rts_pstor/built-in.o:(.text+0x2b96a): first defined here drivers/staging/rts5139/built-in.o: In function `release_xd_card': (.text+0x14393): multiple definition of `release_xd_card' drivers/staging/rts_pstor/built-in.o:(.text+0x2c491): first defined here drivers/staging/rts5139/built-in.o: In function `set_sense_data': (.text+0x1e02): multiple definition of `set_sense_data' drivers/staging/rts_pstor/built-in.o:(.text+0xa79f): first defined here drivers/staging/rts5139/built-in.o: In function `ms_delay_write': ... Signed-off-by: Roger Tseng <rogerable@realtek.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
940 lines
23 KiB
C
940 lines
23 KiB
C
/* Driver for Realtek RTS51xx USB card reader
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*
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* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* wwang (wei_wang@realsil.com.cn)
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* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
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* Maintainer:
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* Edwin Rong (edwin_rong@realsil.com.cn)
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* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
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*/
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#include <linux/blkdev.h>
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#include <linux/kthread.h>
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#include <linux/sched.h>
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#include <linux/workqueue.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_eh.h>
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#include <scsi/scsi_device.h>
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#include "debug.h"
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#include "rts51x.h"
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#include "rts51x_chip.h"
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#include "rts51x_card.h"
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#include "rts51x_transport.h"
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#include "xd.h"
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#include "sd.h"
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#include "ms.h"
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void rts51x_do_remaining_work(struct rts51x_chip *chip)
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{
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struct sd_info *sd_card = &(chip->sd_card);
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struct xd_info *xd_card = &(chip->xd_card);
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struct ms_info *ms_card = &(chip->ms_card);
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if (chip->card_ready & SD_CARD) {
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if (sd_card->seq_mode) {
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RTS51X_SET_STAT(chip, STAT_RUN);
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sd_card->counter++;
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} else {
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sd_card->counter = 0;
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}
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}
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if (chip->card_ready & XD_CARD) {
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if (xd_card->delay_write.delay_write_flag) {
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RTS51X_SET_STAT(chip, STAT_RUN);
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xd_card->counter++;
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} else {
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xd_card->counter = 0;
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}
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}
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if (chip->card_ready & MS_CARD) {
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if (CHK_MSPRO(ms_card)) {
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if (ms_card->seq_mode) {
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RTS51X_SET_STAT(chip, STAT_RUN);
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ms_card->counter++;
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} else {
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ms_card->counter = 0;
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}
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} else {
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if (ms_card->delay_write.delay_write_flag) {
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RTS51X_SET_STAT(chip, STAT_RUN);
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ms_card->counter++;
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} else {
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ms_card->counter = 0;
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}
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}
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}
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if (sd_card->counter > POLLING_WAIT_CNT)
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rts51x_sd_cleanup_work(chip);
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if (xd_card->counter > POLLING_WAIT_CNT)
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rts51x_xd_cleanup_work(chip);
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if (ms_card->counter > POLLING_WAIT_CNT)
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rts51x_ms_cleanup_work(chip);
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}
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static void do_rts51x_reset_xd_card(struct rts51x_chip *chip)
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{
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int retval;
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if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT)
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return;
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retval = rts51x_reset_xd_card(chip);
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if (retval == STATUS_SUCCESS) {
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chip->card_ready |= XD_CARD;
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chip->card_fail &= ~XD_CARD;
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chip->rw_card[chip->card2lun[XD_CARD]] = rts51x_xd_rw;
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} else {
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chip->card_ready &= ~XD_CARD;
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chip->card_fail |= XD_CARD;
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chip->capacity[chip->card2lun[XD_CARD]] = 0;
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chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
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rts51x_init_cmd(chip);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
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POWER_OFF);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
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rts51x_send_cmd(chip, MODE_C, 100);
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}
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}
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void rts51x_do_rts51x_reset_sd_card(struct rts51x_chip *chip)
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{
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int retval;
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if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT)
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return;
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retval = rts51x_reset_sd_card(chip);
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if (retval == STATUS_SUCCESS) {
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chip->card_ready |= SD_CARD;
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chip->card_fail &= ~SD_CARD;
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chip->rw_card[chip->card2lun[SD_CARD]] = rts51x_sd_rw;
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} else {
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chip->card_ready &= ~SD_CARD;
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chip->card_fail |= SD_CARD;
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chip->capacity[chip->card2lun[SD_CARD]] = 0;
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chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
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rts51x_init_cmd(chip);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
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POWER_OFF);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
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rts51x_send_cmd(chip, MODE_C, 100);
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}
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}
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static void do_rts51x_reset_ms_card(struct rts51x_chip *chip)
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{
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int retval;
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if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT)
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return;
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retval = rts51x_reset_ms_card(chip);
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if (retval == STATUS_SUCCESS) {
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chip->card_ready |= MS_CARD;
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chip->card_fail &= ~MS_CARD;
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chip->rw_card[chip->card2lun[MS_CARD]] = rts51x_ms_rw;
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} else {
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chip->card_ready &= ~MS_CARD;
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chip->card_fail |= MS_CARD;
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chip->capacity[chip->card2lun[MS_CARD]] = 0;
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chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
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rts51x_init_cmd(chip);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
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POWER_OFF);
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rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
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rts51x_send_cmd(chip, MODE_C, 100);
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}
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}
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static void card_cd_debounce(struct rts51x_chip *chip, u8 *need_reset,
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u8 *need_release)
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{
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int retval;
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u8 release_map = 0, reset_map = 0;
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u8 value;
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retval = rts51x_get_card_status(chip, &(chip->card_status));
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#ifdef SUPPORT_OCP
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chip->ocp_stat = (chip->card_status >> 4) & 0x03;
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#endif
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if (retval != STATUS_SUCCESS)
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goto Exit_Debounce;
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if (chip->card_exist) {
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retval = rts51x_read_register(chip, CARD_INT_PEND, &value);
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if (retval != STATUS_SUCCESS) {
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rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
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FIFO_FLUSH);
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rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
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value = 0;
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}
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if (chip->card_exist & XD_CARD) {
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if (!(chip->card_status & XD_CD))
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release_map |= XD_CARD;
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} else if (chip->card_exist & SD_CARD) {
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/* if (!(chip->card_status & SD_CD)) { */
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if (!(chip->card_status & SD_CD) || (value & SD_INT))
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release_map |= SD_CARD;
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} else if (chip->card_exist & MS_CARD) {
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/* if (!(chip->card_status & MS_CD)) { */
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if (!(chip->card_status & MS_CD) || (value & MS_INT))
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release_map |= MS_CARD;
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}
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} else {
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if (chip->card_status & XD_CD)
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reset_map |= XD_CARD;
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else if (chip->card_status & SD_CD)
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reset_map |= SD_CARD;
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else if (chip->card_status & MS_CD)
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reset_map |= MS_CARD;
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}
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if (CHECK_PKG(chip, QFN24) && reset_map) {
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if (chip->card_exist & XD_CARD) {
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reset_map = 0;
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goto Exit_Debounce;
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}
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}
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if (reset_map) {
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int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
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int i;
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for (i = 0; i < (chip->option.debounce_num); i++) {
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retval =
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rts51x_get_card_status(chip, &(chip->card_status));
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if (retval != STATUS_SUCCESS) {
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reset_map = release_map = 0;
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goto Exit_Debounce;
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}
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if (chip->card_status & XD_CD)
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xd_cnt++;
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else
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xd_cnt = 0;
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if (chip->card_status & SD_CD)
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sd_cnt++;
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else
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sd_cnt = 0;
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if (chip->card_status & MS_CD)
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ms_cnt++;
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else
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ms_cnt = 0;
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wait_timeout(30);
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}
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reset_map = 0;
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if (!(chip->card_exist & XD_CARD)
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&& (xd_cnt > (chip->option.debounce_num - 1))) {
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reset_map |= XD_CARD;
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}
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if (!(chip->card_exist & SD_CARD)
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&& (sd_cnt > (chip->option.debounce_num - 1))) {
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reset_map |= SD_CARD;
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}
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if (!(chip->card_exist & MS_CARD)
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&& (ms_cnt > (chip->option.debounce_num - 1))) {
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reset_map |= MS_CARD;
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}
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}
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rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
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XD_INT | MS_INT | SD_INT);
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Exit_Debounce:
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if (need_reset)
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*need_reset = reset_map;
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if (need_release)
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*need_release = release_map;
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}
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void rts51x_init_cards(struct rts51x_chip *chip)
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{
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u8 need_reset = 0, need_release = 0;
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card_cd_debounce(chip, &need_reset, &need_release);
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if (need_release) {
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RTS51X_DEBUGP("need_release = 0x%x\n", need_release);
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rts51x_prepare_run(chip);
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RTS51X_SET_STAT(chip, STAT_RUN);
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#ifdef SUPPORT_OCP
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if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
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rts51x_write_register(chip, OCPCTL, MS_OCP_CLEAR,
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MS_OCP_CLEAR);
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chip->ocp_stat = 0;
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RTS51X_DEBUGP("Clear OCP status.\n");
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}
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#endif
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if (need_release & XD_CARD) {
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chip->card_exist &= ~XD_CARD;
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chip->card_ejected = 0;
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if (chip->card_ready & XD_CARD) {
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rts51x_release_xd_card(chip);
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chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
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clear_bit(chip->card2lun[XD_CARD],
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&(chip->lun_mc));
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}
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}
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if (need_release & SD_CARD) {
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chip->card_exist &= ~SD_CARD;
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chip->card_ejected = 0;
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if (chip->card_ready & SD_CARD) {
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rts51x_release_sd_card(chip);
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chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
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clear_bit(chip->card2lun[SD_CARD],
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&(chip->lun_mc));
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}
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}
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if (need_release & MS_CARD) {
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chip->card_exist &= ~MS_CARD;
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chip->card_ejected = 0;
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if (chip->card_ready & MS_CARD) {
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rts51x_release_ms_card(chip);
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chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
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clear_bit(chip->card2lun[MS_CARD],
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&(chip->lun_mc));
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}
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}
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}
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if (need_reset && !chip->card_ready) {
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RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset);
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rts51x_prepare_run(chip);
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RTS51X_SET_STAT(chip, STAT_RUN);
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if (need_reset & XD_CARD) {
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chip->card_exist |= XD_CARD;
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do_rts51x_reset_xd_card(chip);
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} else if (need_reset & SD_CARD) {
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chip->card_exist |= SD_CARD;
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rts51x_do_rts51x_reset_sd_card(chip);
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} else if (need_reset & MS_CARD) {
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chip->card_exist |= MS_CARD;
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do_rts51x_reset_ms_card(chip);
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}
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}
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}
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void rts51x_release_cards(struct rts51x_chip *chip)
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{
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if (chip->card_ready & SD_CARD) {
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rts51x_sd_cleanup_work(chip);
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rts51x_release_sd_card(chip);
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chip->card_ready &= ~SD_CARD;
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}
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if (chip->card_ready & XD_CARD) {
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rts51x_xd_cleanup_work(chip);
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rts51x_release_xd_card(chip);
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chip->card_ready &= ~XD_CARD;
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}
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if (chip->card_ready & MS_CARD) {
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rts51x_ms_cleanup_work(chip);
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rts51x_release_ms_card(chip);
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chip->card_ready &= ~MS_CARD;
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}
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}
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static inline u8 double_depth(u8 depth)
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{
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return ((depth > 1) ? (depth - 1) : depth);
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}
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int rts51x_switch_ssc_clock(struct rts51x_chip *chip, int clk)
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{
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struct sd_info *sd_card = &(chip->sd_card);
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struct ms_info *ms_card = &(chip->ms_card);
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int retval;
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u8 N = (u8) (clk - 2), min_N, max_N;
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u8 mcu_cnt, div, max_div, ssc_depth;
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int sd_vpclk_phase_reset = 0;
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if (chip->cur_clk == clk)
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return STATUS_SUCCESS;
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min_N = 60;
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max_N = 120;
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max_div = CLK_DIV_4;
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RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk);
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if ((clk <= 2) || (N > max_N))
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TRACE_RET(chip, STATUS_FAIL);
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mcu_cnt = (u8) (60 / clk + 3);
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if (mcu_cnt > 15)
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mcu_cnt = 15;
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/* To make sure that the SSC clock div_n is
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* equal or greater than min_N */
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div = CLK_DIV_1;
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while ((N < min_N) && (div < max_div)) {
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N = (N + 2) * 2 - 2;
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div++;
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}
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RTS51X_DEBUGP("N = %d, div = %d\n", N, div);
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if (chip->option.ssc_en) {
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if (chip->cur_card == SD_CARD) {
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if (CHK_SD_SDR104(sd_card)) {
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ssc_depth = chip->option.ssc_depth_sd_sdr104;
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} else if (CHK_SD_SDR50(sd_card)) {
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ssc_depth = chip->option.ssc_depth_sd_sdr50;
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} else if (CHK_SD_DDR50(sd_card)) {
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ssc_depth =
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double_depth(chip->option.
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ssc_depth_sd_ddr50);
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} else if (CHK_SD_HS(sd_card)) {
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ssc_depth =
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double_depth(chip->option.ssc_depth_sd_hs);
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} else if (CHK_MMC_52M(sd_card)
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|| CHK_MMC_DDR52(sd_card)) {
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ssc_depth =
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double_depth(chip->option.
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ssc_depth_mmc_52m);
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} else {
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ssc_depth =
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double_depth(chip->option.
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ssc_depth_low_speed);
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}
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} else if (chip->cur_card == MS_CARD) {
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if (CHK_MSPRO(ms_card)) {
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if (CHK_HG8BIT(ms_card)) {
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ssc_depth =
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double_depth(chip->option.
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ssc_depth_ms_hg);
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} else {
|
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ssc_depth =
|
|
double_depth(chip->option.
|
|
ssc_depth_ms_4bit);
|
|
}
|
|
} else {
|
|
if (CHK_MS4BIT(ms_card)) {
|
|
ssc_depth =
|
|
double_depth(chip->option.
|
|
ssc_depth_ms_4bit);
|
|
} else {
|
|
ssc_depth =
|
|
double_depth(chip->option.
|
|
ssc_depth_low_speed);
|
|
}
|
|
}
|
|
} else {
|
|
ssc_depth =
|
|
double_depth(chip->option.ssc_depth_low_speed);
|
|
}
|
|
|
|
if (ssc_depth) {
|
|
if (div == CLK_DIV_2) {
|
|
/* If clock divided by 2, ssc depth must
|
|
* be multiplied by 2 */
|
|
if (ssc_depth > 1)
|
|
ssc_depth -= 1;
|
|
else
|
|
ssc_depth = SSC_DEPTH_2M;
|
|
} else if (div == CLK_DIV_4) {
|
|
/* If clock divided by 4, ssc depth must
|
|
* be multiplied by 4 */
|
|
if (ssc_depth > 2)
|
|
ssc_depth -= 2;
|
|
else
|
|
ssc_depth = SSC_DEPTH_2M;
|
|
}
|
|
}
|
|
} else {
|
|
/* Disable SSC */
|
|
ssc_depth = 0;
|
|
}
|
|
|
|
RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth);
|
|
|
|
rts51x_init_cmd(chip);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
|
|
(div << 4) | mcu_cnt);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK,
|
|
ssc_depth);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
|
|
if (sd_vpclk_phase_reset) {
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
|
|
PHASE_NOT_RESET, 0);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
|
|
PHASE_NOT_RESET, PHASE_NOT_RESET);
|
|
}
|
|
|
|
retval = rts51x_send_cmd(chip, MODE_C, 2000);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, retval);
|
|
if (chip->option.ssc_en && ssc_depth)
|
|
rts51x_write_register(chip, SSC_CTL1, 0xff, 0xD0);
|
|
else
|
|
rts51x_write_register(chip, SSC_CTL1, 0xff, 0x50);
|
|
udelay(100);
|
|
RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
|
|
|
|
chip->cur_clk = clk;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int rts51x_switch_normal_clock(struct rts51x_chip *chip, int clk)
|
|
{
|
|
int retval;
|
|
u8 sel, div, mcu_cnt;
|
|
int sd_vpclk_phase_reset = 0;
|
|
|
|
if (chip->cur_clk == clk)
|
|
return STATUS_SUCCESS;
|
|
|
|
if (chip->cur_card == SD_CARD) {
|
|
struct sd_info *sd_card = &(chip->sd_card);
|
|
if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
|
|
sd_vpclk_phase_reset = 1;
|
|
}
|
|
|
|
switch (clk) {
|
|
case CLK_20:
|
|
RTS51X_DEBUGP("Switch clock to 20MHz\n");
|
|
sel = SSC_80;
|
|
div = CLK_DIV_4;
|
|
mcu_cnt = 5;
|
|
break;
|
|
|
|
case CLK_30:
|
|
RTS51X_DEBUGP("Switch clock to 30MHz\n");
|
|
sel = SSC_60;
|
|
div = CLK_DIV_2;
|
|
mcu_cnt = 4;
|
|
break;
|
|
|
|
case CLK_40:
|
|
RTS51X_DEBUGP("Switch clock to 40MHz\n");
|
|
sel = SSC_80;
|
|
div = CLK_DIV_2;
|
|
mcu_cnt = 3;
|
|
break;
|
|
|
|
case CLK_50:
|
|
RTS51X_DEBUGP("Switch clock to 50MHz\n");
|
|
sel = SSC_100;
|
|
div = CLK_DIV_2;
|
|
mcu_cnt = 3;
|
|
break;
|
|
|
|
case CLK_60:
|
|
RTS51X_DEBUGP("Switch clock to 60MHz\n");
|
|
sel = SSC_60;
|
|
div = CLK_DIV_1;
|
|
mcu_cnt = 3;
|
|
break;
|
|
|
|
case CLK_80:
|
|
RTS51X_DEBUGP("Switch clock to 80MHz\n");
|
|
sel = SSC_80;
|
|
div = CLK_DIV_1;
|
|
mcu_cnt = 2;
|
|
break;
|
|
|
|
case CLK_100:
|
|
RTS51X_DEBUGP("Switch clock to 100MHz\n");
|
|
sel = SSC_100;
|
|
div = CLK_DIV_1;
|
|
mcu_cnt = 2;
|
|
break;
|
|
|
|
/* case CLK_120:
|
|
RTS51X_DEBUGP("Switch clock to 120MHz\n");
|
|
sel = SSC_120;
|
|
div = CLK_DIV_1;
|
|
mcu_cnt = 2;
|
|
break;
|
|
|
|
case CLK_150:
|
|
RTS51X_DEBUGP("Switch clock to 150MHz\n");
|
|
sel = SSC_150;
|
|
div = CLK_DIV_1;
|
|
mcu_cnt = 2;
|
|
break; */
|
|
|
|
default:
|
|
RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
|
|
clk);
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
}
|
|
|
|
if (!sd_vpclk_phase_reset) {
|
|
rts51x_init_cmd(chip);
|
|
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
|
|
CLK_CHANGE);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
|
|
(div << 4) | mcu_cnt);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
|
|
sel);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
|
|
|
|
retval = rts51x_send_cmd(chip, MODE_C, 100);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, retval);
|
|
} else {
|
|
rts51x_init_cmd(chip);
|
|
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
|
|
CLK_CHANGE);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
|
|
PHASE_NOT_RESET, 0);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
|
|
PHASE_NOT_RESET, 0);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
|
|
(div << 4) | mcu_cnt);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
|
|
sel);
|
|
|
|
retval = rts51x_send_cmd(chip, MODE_C, 100);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, retval);
|
|
|
|
udelay(200);
|
|
|
|
rts51x_init_cmd(chip);
|
|
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
|
|
PHASE_NOT_RESET, PHASE_NOT_RESET);
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
|
|
PHASE_NOT_RESET, PHASE_NOT_RESET);
|
|
|
|
retval = rts51x_send_cmd(chip, MODE_C, 100);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, retval);
|
|
|
|
udelay(200);
|
|
|
|
RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
|
|
}
|
|
|
|
chip->cur_clk = clk;
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int rts51x_card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr,
|
|
u16 sec_cnt)
|
|
{
|
|
int retval;
|
|
unsigned int lun = SCSI_LUN(srb);
|
|
int i;
|
|
|
|
if (chip->rw_card[lun] == NULL)
|
|
return STATUS_FAIL;
|
|
|
|
RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
|
|
(srb->sc_data_direction ==
|
|
DMA_TO_DEVICE) ? "Write" : "Read", sec_addr, sec_cnt);
|
|
|
|
chip->rw_need_retry = 0;
|
|
for (i = 0; i < 3; i++) {
|
|
retval = chip->rw_card[lun] (srb, chip, sec_addr, sec_cnt);
|
|
if (retval != STATUS_SUCCESS) {
|
|
CATCH_TRIGGER(chip);
|
|
if (chip->option.reset_or_rw_fail_set_pad_drive) {
|
|
rts51x_write_register(chip, CARD_DRIVE_SEL,
|
|
SD20_DRIVE_MASK,
|
|
DRIVE_8mA);
|
|
}
|
|
}
|
|
|
|
if (!chip->rw_need_retry)
|
|
break;
|
|
|
|
RTS51X_DEBUGP("Retry RW, (i = %d\n)", i);
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
u8 rts51x_get_lun_card(struct rts51x_chip *chip, unsigned int lun)
|
|
{
|
|
if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
|
|
return (u8) XD_CARD;
|
|
else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
|
|
return (u8) SD_CARD;
|
|
else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
|
|
return (u8) MS_CARD;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int card_share_mode(struct rts51x_chip *chip, int card)
|
|
{
|
|
u8 value;
|
|
|
|
if (card == SD_CARD)
|
|
value = CARD_SHARE_SD;
|
|
else if (card == MS_CARD)
|
|
value = CARD_SHARE_MS;
|
|
else if (card == XD_CARD)
|
|
value = CARD_SHARE_XD;
|
|
else
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
|
|
RTS51X_WRITE_REG(chip, CARD_SHARE_MODE, CARD_SHARE_MASK, value);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int rts51x_select_card(struct rts51x_chip *chip, int card)
|
|
{
|
|
int retval;
|
|
|
|
if (chip->cur_card != card) {
|
|
u8 mod;
|
|
|
|
if (card == SD_CARD)
|
|
mod = SD_MOD_SEL;
|
|
else if (card == MS_CARD)
|
|
mod = MS_MOD_SEL;
|
|
else if (card == XD_CARD)
|
|
mod = XD_MOD_SEL;
|
|
else
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
RTS51X_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
|
|
chip->cur_card = card;
|
|
|
|
retval = card_share_mode(chip, card);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, retval);
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
void rts51x_eject_card(struct rts51x_chip *chip, unsigned int lun)
|
|
{
|
|
RTS51X_DEBUGP("eject card\n");
|
|
RTS51X_SET_STAT(chip, STAT_RUN);
|
|
rts51x_do_remaining_work(chip);
|
|
|
|
if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
|
|
rts51x_release_sd_card(chip);
|
|
chip->card_ejected |= SD_CARD;
|
|
chip->card_ready &= ~SD_CARD;
|
|
chip->capacity[lun] = 0;
|
|
} else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
|
|
rts51x_release_xd_card(chip);
|
|
chip->card_ejected |= XD_CARD;
|
|
chip->card_ready &= ~XD_CARD;
|
|
chip->capacity[lun] = 0;
|
|
} else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
|
|
rts51x_release_ms_card(chip);
|
|
chip->card_ejected |= MS_CARD;
|
|
chip->card_ready &= ~MS_CARD;
|
|
chip->capacity[lun] = 0;
|
|
}
|
|
rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
|
|
XD_INT | MS_INT | SD_INT);
|
|
}
|
|
|
|
void rts51x_trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip,
|
|
u32 byte_cnt, u8 pack_size)
|
|
{
|
|
if (pack_size > DMA_1024)
|
|
pack_size = DMA_512;
|
|
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
|
|
RING_BUFFER);
|
|
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC3, 0xFF,
|
|
(u8) (byte_cnt >> 24));
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC2, 0xFF,
|
|
(u8) (byte_cnt >> 16));
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC1, 0xFF,
|
|
(u8) (byte_cnt >> 8));
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC0, 0xFF, (u8) byte_cnt);
|
|
|
|
if (dir == DMA_FROM_DEVICE) {
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
|
|
0x03 | DMA_PACK_SIZE_MASK,
|
|
DMA_DIR_FROM_CARD | DMA_EN | pack_size);
|
|
} else {
|
|
rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
|
|
0x03 | DMA_PACK_SIZE_MASK,
|
|
DMA_DIR_TO_CARD | DMA_EN | pack_size);
|
|
}
|
|
}
|
|
|
|
int rts51x_enable_card_clock(struct rts51x_chip *chip, u8 card)
|
|
{
|
|
u8 clk_en = 0;
|
|
|
|
if (card & XD_CARD)
|
|
clk_en |= XD_CLK_EN;
|
|
if (card & SD_CARD)
|
|
clk_en |= SD_CLK_EN;
|
|
if (card & MS_CARD)
|
|
clk_en |= MS_CLK_EN;
|
|
|
|
RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int rts51x_card_power_on(struct rts51x_chip *chip, u8 card)
|
|
{
|
|
u8 mask, val1, val2;
|
|
|
|
mask = POWER_MASK;
|
|
val1 = PARTIAL_POWER_ON;
|
|
val2 = POWER_ON;
|
|
|
|
#ifdef SD_XD_IO_FOLLOW_PWR
|
|
if ((card == SD_CARD) || (card == XD_CARD)) {
|
|
RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask | LDO3318_PWR_MASK,
|
|
val1 | LDO_SUSPEND);
|
|
} else {
|
|
#endif
|
|
RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val1);
|
|
#ifdef SD_XD_IO_FOLLOW_PWR
|
|
}
|
|
#endif
|
|
udelay(chip->option.pwr_delay);
|
|
RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val2);
|
|
#ifdef SD_XD_IO_FOLLOW_PWR
|
|
if (card == SD_CARD) {
|
|
rts51x_write_register(chip, CARD_PWR_CTL, LDO3318_PWR_MASK,
|
|
LDO_ON);
|
|
}
|
|
#endif
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int monitor_card_cd(struct rts51x_chip *chip, u8 card)
|
|
{
|
|
int retval;
|
|
u8 card_cd[32] = { 0 };
|
|
|
|
card_cd[SD_CARD] = SD_CD;
|
|
card_cd[XD_CARD] = XD_CD;
|
|
card_cd[MS_CARD] = MS_CD;
|
|
|
|
retval = rts51x_get_card_status(chip, &(chip->card_status));
|
|
if (retval != STATUS_SUCCESS)
|
|
return CD_NOT_EXIST;
|
|
|
|
if (chip->card_status & card_cd[card])
|
|
return CD_EXIST;
|
|
|
|
return CD_NOT_EXIST;
|
|
}
|
|
|
|
int rts51x_toggle_gpio(struct rts51x_chip *chip, u8 gpio)
|
|
{
|
|
int retval;
|
|
u8 temp_reg;
|
|
u8 gpio_output[4] = {
|
|
0x01,
|
|
};
|
|
u8 gpio_oe[4] = {
|
|
0x02,
|
|
};
|
|
if (chip->rts5179) {
|
|
retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
temp_reg ^= gpio_oe[gpio];
|
|
temp_reg &= 0xfe; /* bit 0 always set 0 */
|
|
retval =
|
|
rts51x_ep0_write_register(chip, CARD_GPIO, 0x03, temp_reg);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
} else {
|
|
retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
temp_reg ^= gpio_output[gpio];
|
|
retval =
|
|
rts51x_ep0_write_register(chip, CARD_GPIO, 0xFF,
|
|
temp_reg | gpio_oe[gpio]);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int rts51x_turn_on_led(struct rts51x_chip *chip, u8 gpio)
|
|
{
|
|
int retval;
|
|
u8 gpio_oe[4] = {
|
|
0x02,
|
|
};
|
|
u8 gpio_mask[4] = {
|
|
0x03,
|
|
};
|
|
|
|
retval =
|
|
rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
|
|
gpio_oe[gpio]);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|
|
|
|
int rts51x_turn_off_led(struct rts51x_chip *chip, u8 gpio)
|
|
{
|
|
int retval;
|
|
u8 gpio_output[4] = {
|
|
0x01,
|
|
};
|
|
u8 gpio_oe[4] = {
|
|
0x02,
|
|
};
|
|
u8 gpio_mask[4] = {
|
|
0x03,
|
|
};
|
|
|
|
retval =
|
|
rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
|
|
gpio_oe[gpio] | gpio_output[gpio]);
|
|
if (retval != STATUS_SUCCESS)
|
|
TRACE_RET(chip, STATUS_FAIL);
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|