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5deb67f77a
mmio_flush_range() suffers from a lack of clearly-defined semantics,
and is somewhat ambiguous to port to other architectures where the
scope of the writeback implied by "flush" and ordering might matter,
but MMIO would tend to imply non-cacheable anyway. Per the rationale
in 67a3e8fe90 ("nd_blk: change aperture mapping from WC to WB"), the
only existing use is actually to invalidate clean cache lines for
ARCH_MEMREMAP_PMEM type mappings *without* writeback. Since the recent
cleanup of the pmem API, that also now happens to be the exact purpose
of arch_invalidate_pmem(), which would be a far more well-defined tool
for the job.
Rather than risk potentially inconsistent implementations of
mmio_flush_range() for the sake of one callsite, streamline things by
removing it entirely and instead move the ARCH_MEMREMAP_PMEM related
definitions up to the libnvdimm level, so they can be shared by NFIT
as well. This allows NFIT to be enabled for arm64.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
10 lines
267 B
C
10 lines
267 B
C
#ifndef _ASM_X86_CACHEFLUSH_H
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#define _ASM_X86_CACHEFLUSH_H
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/* Caches aren't brain-dead on the intel. */
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#include <asm-generic/cacheflush.h>
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#include <asm/special_insns.h>
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void clflush_cache_range(void *addr, unsigned int size);
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#endif /* _ASM_X86_CACHEFLUSH_H */
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