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![Jacob Shin](/assets/img/avatar_default.png)
Implement hardware breakpoint address mask for AMD Family 16h and above processors. CPUID feature bit indicates hardware support for DRn_ADDR_MASK MSRs. These masks further qualify DRn/DR7 hardware breakpoint addresses to allow matching of larger addresses ranges. Valuable advice and pseudo code from Oleg Nesterov <oleg@redhat.com> Signed-off-by: Jacob Shin <jacob.w.shin@gmail.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Acked-by: Jiri Olsa <jolsa@kernel.org> Reviewed-by: Oleg Nesterov <oleg@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: Ingo Molnar <mingo@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: xiakaixu <xiakaixu@huawei.com> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com>
123 lines
2.6 KiB
C
123 lines
2.6 KiB
C
#ifndef _ASM_X86_DEBUGREG_H
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#define _ASM_X86_DEBUGREG_H
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#include <linux/bug.h>
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#include <uapi/asm/debugreg.h>
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DECLARE_PER_CPU(unsigned long, cpu_dr7);
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#ifndef CONFIG_PARAVIRT
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/*
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* These special macros can be used to get or set a debugging register
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*/
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#define get_debugreg(var, register) \
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(var) = native_get_debugreg(register)
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#define set_debugreg(value, register) \
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native_set_debugreg(register, value)
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#endif
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static inline unsigned long native_get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("mov %%db0, %0" :"=r" (val));
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break;
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case 1:
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asm("mov %%db1, %0" :"=r" (val));
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break;
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case 2:
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asm("mov %%db2, %0" :"=r" (val));
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break;
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case 3:
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asm("mov %%db3, %0" :"=r" (val));
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break;
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case 6:
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asm("mov %%db6, %0" :"=r" (val));
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break;
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case 7:
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asm("mov %%db7, %0" :"=r" (val));
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break;
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default:
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BUG();
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}
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return val;
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}
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static inline void native_set_debugreg(int regno, unsigned long value)
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{
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switch (regno) {
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case 0:
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asm("mov %0, %%db0" ::"r" (value));
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break;
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case 1:
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asm("mov %0, %%db1" ::"r" (value));
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break;
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case 2:
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asm("mov %0, %%db2" ::"r" (value));
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break;
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case 3:
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asm("mov %0, %%db3" ::"r" (value));
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break;
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case 6:
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asm("mov %0, %%db6" ::"r" (value));
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break;
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case 7:
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asm("mov %0, %%db7" ::"r" (value));
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break;
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default:
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BUG();
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}
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}
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static inline void hw_breakpoint_disable(void)
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{
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/* Zero the control register for HW Breakpoint */
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set_debugreg(0UL, 7);
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/* Zero-out the individual HW breakpoint address registers */
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set_debugreg(0UL, 0);
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set_debugreg(0UL, 1);
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set_debugreg(0UL, 2);
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set_debugreg(0UL, 3);
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}
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static inline int hw_breakpoint_active(void)
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{
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return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
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}
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extern void aout_dump_debugregs(struct user *dump);
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extern void hw_breakpoint_restore(void);
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#ifdef CONFIG_X86_64
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DECLARE_PER_CPU(int, debug_stack_usage);
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static inline void debug_stack_usage_inc(void)
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{
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__this_cpu_inc(debug_stack_usage);
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}
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static inline void debug_stack_usage_dec(void)
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{
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__this_cpu_dec(debug_stack_usage);
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}
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int is_debug_stack(unsigned long addr);
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void debug_stack_set_zero(void);
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void debug_stack_reset(void);
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#else /* !X86_64 */
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static inline int is_debug_stack(unsigned long addr) { return 0; }
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static inline void debug_stack_set_zero(void) { }
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static inline void debug_stack_reset(void) { }
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static inline void debug_stack_usage_inc(void) { }
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static inline void debug_stack_usage_dec(void) { }
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#endif /* X86_64 */
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#ifdef CONFIG_CPU_SUP_AMD
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extern void set_dr_addr_mask(unsigned long mask, int dr);
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#else
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static inline void set_dr_addr_mask(unsigned long mask, int dr) { }
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#endif
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#endif /* _ASM_X86_DEBUGREG_H */
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