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c7753208a9
Since DMA addresses will effectively look like 48-bit addresses when the memory encryption mask is set, SWIOTLB is needed if the DMA mask of the device performing the DMA does not support 48-bits. SWIOTLB will be initialized to create decrypted bounce buffers for use by these devices. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Ryabinin <aryabinin@virtuozzo.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Dave Young <dyoung@redhat.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Larry Woodman <lwoodman@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matt Fleming <matt@codeblueprint.co.uk> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Rik van Riel <riel@redhat.com> Cc: Toshimitsu Kani <toshi.kani@hpe.com> Cc: kasan-dev@googlegroups.com Cc: kvm@vger.kernel.org Cc: linux-arch@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-efi@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/aa2d29b78ae7d508db8881e46a3215231b9327a7.1500319216.git.thomas.lendacky@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
#ifndef _ASM_X86_DMA_MAPPING_H
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#define _ASM_X86_DMA_MAPPING_H
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/*
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* IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
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* Documentation/DMA-API.txt for documentation.
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*/
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#include <linux/kmemcheck.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-debug.h>
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#include <asm/io.h>
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#include <asm/swiotlb.h>
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#include <linux/dma-contiguous.h>
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#include <linux/mem_encrypt.h>
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#ifdef CONFIG_ISA
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
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#else
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
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#endif
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extern int iommu_merge;
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extern struct device x86_dma_fallback_dev;
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extern int panic_on_overflow;
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extern const struct dma_map_ops *dma_ops;
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static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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{
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return dma_ops;
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}
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bool arch_dma_alloc_attrs(struct device **dev, gfp_t *gfp);
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#define arch_dma_alloc_attrs arch_dma_alloc_attrs
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extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addr, gfp_t flag,
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unsigned long attrs);
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extern void dma_generic_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_addr,
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unsigned long attrs);
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#ifdef CONFIG_X86_DMA_REMAP /* Platform code defines bridge-specific code */
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extern bool dma_capable(struct device *dev, dma_addr_t addr, size_t size);
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extern dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
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extern phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
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#else
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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return 0;
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return addr + size - 1 <= *dev->dma_mask;
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return __sme_set(paddr);
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}
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static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return __sme_clr(daddr);
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}
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#endif /* CONFIG_X86_DMA_REMAP */
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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flush_write_buffers();
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}
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static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
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gfp_t gfp)
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{
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unsigned long dma_mask = 0;
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dma_mask = dev->coherent_dma_mask;
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if (!dma_mask)
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dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
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return dma_mask;
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}
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static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
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{
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unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
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if (dma_mask <= DMA_BIT_MASK(24))
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gfp |= GFP_DMA;
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#ifdef CONFIG_X86_64
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if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
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gfp |= GFP_DMA32;
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#endif
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return gfp;
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}
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#endif
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