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25af37f4e1
Add support for Intel's AVX-512 instructions to the instruction decoder. AVX-512 instructions are documented in Intel Architecture Instruction Set Extensions Programming Reference (February 2016). AVX-512 instructions are identified by a EVEX prefix which, for the purpose of instruction decoding, can be treated as though it were a 4-byte VEX prefix. Existing instructions which can now accept an EVEX prefix need not be further annotated in the op code map (x86-opcode-map.txt). In the case of new instructions, the op code map is updated accordingly. Also add associated Mask Instructions that are used to manipulate mask registers used in AVX-512 instructions. The 'perf tools' instruction decoder is updated in a subsequent patch. And a representative set of instructions is added to the perf tools new instructions test in a subsequent patch. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dan Williams <dan.j.williams@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: X86 ML <x86@kernel.org> Link: http://lkml.kernel.org/r/1469003437-32706-3-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
211 lines
6.3 KiB
C
211 lines
6.3 KiB
C
#ifndef _ASM_X86_INSN_H
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#define _ASM_X86_INSN_H
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/*
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* x86 instruction analysis
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2009
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*/
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/* insn_attr_t is defined in inat.h */
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#include <asm/inat.h>
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struct insn_field {
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union {
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insn_value_t value;
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insn_byte_t bytes[4];
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};
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/* !0 if we've run insn_get_xxx() for this field */
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unsigned char got;
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unsigned char nbytes;
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};
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struct insn {
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struct insn_field prefixes; /*
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* Prefixes
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* prefixes.bytes[3]: last prefix
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*/
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struct insn_field rex_prefix; /* REX prefix */
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struct insn_field vex_prefix; /* VEX prefix */
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struct insn_field opcode; /*
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* opcode.bytes[0]: opcode1
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* opcode.bytes[1]: opcode2
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* opcode.bytes[2]: opcode3
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*/
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struct insn_field modrm;
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struct insn_field sib;
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struct insn_field displacement;
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union {
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struct insn_field immediate;
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struct insn_field moffset1; /* for 64bit MOV */
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struct insn_field immediate1; /* for 64bit imm or off16/32 */
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};
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union {
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struct insn_field moffset2; /* for 64bit MOV */
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struct insn_field immediate2; /* for 64bit imm or seg16 */
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};
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insn_attr_t attr;
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unsigned char opnd_bytes;
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unsigned char addr_bytes;
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unsigned char length;
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unsigned char x86_64;
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const insn_byte_t *kaddr; /* kernel address of insn to analyze */
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const insn_byte_t *end_kaddr; /* kernel address of last insn in buffer */
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const insn_byte_t *next_byte;
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};
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#define MAX_INSN_SIZE 15
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#define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
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#define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
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#define X86_MODRM_RM(modrm) ((modrm) & 0x07)
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#define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
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#define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
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#define X86_SIB_BASE(sib) ((sib) & 0x07)
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#define X86_REX_W(rex) ((rex) & 8)
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#define X86_REX_R(rex) ((rex) & 4)
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#define X86_REX_X(rex) ((rex) & 2)
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#define X86_REX_B(rex) ((rex) & 1)
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/* VEX bit flags */
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#define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
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#define X86_VEX_R(vex) ((vex) & 0x80) /* VEX2/3 Byte1 */
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#define X86_VEX_X(vex) ((vex) & 0x40) /* VEX3 Byte1 */
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#define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */
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#define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */
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/* VEX bit fields */
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#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */
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#define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */
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#define X86_VEX2_M 1 /* VEX2.M always 1 */
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#define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */
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#define X86_VEX_P(vex) ((vex) & 0x03) /* VEX3 Byte2, VEX2 Byte1 */
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#define X86_VEX_M_MAX 0x1f /* VEX3.M Maximum value */
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extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
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extern void insn_get_prefixes(struct insn *insn);
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extern void insn_get_opcode(struct insn *insn);
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extern void insn_get_modrm(struct insn *insn);
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extern void insn_get_sib(struct insn *insn);
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extern void insn_get_displacement(struct insn *insn);
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extern void insn_get_immediate(struct insn *insn);
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extern void insn_get_length(struct insn *insn);
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/* Attribute will be determined after getting ModRM (for opcode groups) */
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static inline void insn_get_attribute(struct insn *insn)
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{
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insn_get_modrm(insn);
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}
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/* Instruction uses RIP-relative addressing */
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extern int insn_rip_relative(struct insn *insn);
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/* Init insn for kernel text */
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static inline void kernel_insn_init(struct insn *insn,
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const void *kaddr, int buf_len)
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{
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#ifdef CONFIG_X86_64
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insn_init(insn, kaddr, buf_len, 1);
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#else /* CONFIG_X86_32 */
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insn_init(insn, kaddr, buf_len, 0);
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#endif
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}
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static inline int insn_is_avx(struct insn *insn)
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{
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if (!insn->prefixes.got)
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insn_get_prefixes(insn);
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return (insn->vex_prefix.value != 0);
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}
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static inline int insn_is_evex(struct insn *insn)
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{
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if (!insn->prefixes.got)
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insn_get_prefixes(insn);
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return (insn->vex_prefix.nbytes == 4);
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}
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/* Ensure this instruction is decoded completely */
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static inline int insn_complete(struct insn *insn)
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{
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return insn->opcode.got && insn->modrm.got && insn->sib.got &&
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insn->displacement.got && insn->immediate.got;
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}
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static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
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{
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if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
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return X86_VEX2_M;
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else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */
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return X86_VEX3_M(insn->vex_prefix.bytes[1]);
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else /* EVEX */
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return X86_EVEX_M(insn->vex_prefix.bytes[1]);
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}
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static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
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{
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if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
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return X86_VEX_P(insn->vex_prefix.bytes[1]);
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else
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return X86_VEX_P(insn->vex_prefix.bytes[2]);
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}
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/* Get the last prefix id from last prefix or VEX prefix */
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static inline int insn_last_prefix_id(struct insn *insn)
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{
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if (insn_is_avx(insn))
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return insn_vex_p_bits(insn); /* VEX_p is a SIMD prefix id */
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if (insn->prefixes.bytes[3])
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return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
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return 0;
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}
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/* Offset of each field from kaddr */
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static inline int insn_offset_rex_prefix(struct insn *insn)
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{
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return insn->prefixes.nbytes;
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}
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static inline int insn_offset_vex_prefix(struct insn *insn)
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{
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return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
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}
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static inline int insn_offset_opcode(struct insn *insn)
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{
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return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
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}
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static inline int insn_offset_modrm(struct insn *insn)
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{
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return insn_offset_opcode(insn) + insn->opcode.nbytes;
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}
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static inline int insn_offset_sib(struct insn *insn)
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{
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return insn_offset_modrm(insn) + insn->modrm.nbytes;
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}
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static inline int insn_offset_displacement(struct insn *insn)
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{
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return insn_offset_sib(insn) + insn->sib.nbytes;
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}
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static inline int insn_offset_immediate(struct insn *insn)
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{
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return insn_offset_displacement(insn) + insn->displacement.nbytes;
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}
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#endif /* _ASM_X86_INSN_H */
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