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935356cecd
A cold or warm boot through BIOS sets the APIC in default interrupt
delivery mode. A dump-capture kernel will not go through a BIOS reset and
leave the interrupt delivery mode in the state which was active on the
crashed kernel, but the dump kernel startup code assumes default delivery
mode which can result in interrupt delivery/handling to fail.
To solve this problem, it's required to set up the final interrupt delivery
mode as soon as possible. As IOAPIC setup needs the timer initialized for
verifying the timer interrupt delivery mode, the earliest point is right
after timer setup in late_time_init().
That results in the following init order:
1) Set up the legacy timer, if applicable on the platform
2) Set up APIC/IOAPIC which includes the verification of the legacy timer
interrupt delivery.
3) TSC calibration
4) Local APIC timer setup
Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: yinghai@kernel.org
Cc: bhe@redhat.com
Link: https://lkml.kernel.org/r/1505293975-26005-12-git-send-email-douly.fnst@cn.fujitsu.com
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
/*
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* Copyright (c) 1991,1992,1995 Linus Torvalds
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* Copyright (c) 1994 Alan Modra
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* Copyright (c) 1995 Markus Kuhn
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* Copyright (c) 1996 Ingo Molnar
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* Copyright (c) 1998 Andrea Arcangeli
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* Copyright (c) 2002,2006 Vojtech Pavlik
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* Copyright (c) 2003 Andi Kleen
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*
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/i8253.h>
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#include <linux/time.h>
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#include <linux/export.h>
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#include <asm/vsyscall.h>
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#include <asm/x86_init.h>
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#include <asm/i8259.h>
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#include <asm/timer.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#ifdef CONFIG_X86_64
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__visible volatile unsigned long jiffies __cacheline_aligned = INITIAL_JIFFIES;
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#endif
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unsigned long profile_pc(struct pt_regs *regs)
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{
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unsigned long pc = instruction_pointer(regs);
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if (!user_mode(regs) && in_lock_functions(pc)) {
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#ifdef CONFIG_FRAME_POINTER
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return *(unsigned long *)(regs->bp + sizeof(long));
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#else
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unsigned long *sp =
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(unsigned long *)kernel_stack_pointer(regs);
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/*
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* Return address is either directly at stack pointer
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* or above a saved flags. Eflags has bits 22-31 zero,
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* kernel addresses don't.
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*/
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if (sp[0] >> 22)
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return sp[0];
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if (sp[1] >> 22)
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return sp[1];
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#endif
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}
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return pc;
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}
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EXPORT_SYMBOL(profile_pc);
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/*
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* Default timer interrupt handler for PIT/HPET
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*/
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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global_clock_event->event_handler(global_clock_event);
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return IRQ_HANDLED;
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}
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.flags = IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER,
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.name = "timer"
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};
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static void __init setup_default_timer_irq(void)
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{
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if (!nr_legacy_irqs())
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return;
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setup_irq(0, &irq0);
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}
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/* Default timer init function */
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void __init hpet_time_init(void)
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{
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if (!hpet_enable())
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setup_pit_timer();
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setup_default_timer_irq();
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}
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static __init void x86_late_time_init(void)
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{
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x86_init.timers.timer_init();
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/*
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* After PIT/HPET timers init, select and setup
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* the final interrupt mode for delivering IRQs.
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*/
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x86_init.irqs.intr_mode_init();
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tsc_init();
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}
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/*
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* Initialize TSC and delay the periodic timer init to
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* late x86_late_time_init() so ioremap works.
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*/
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void __init time_init(void)
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{
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late_time_init = x86_late_time_init;
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}
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