204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <drm/drm_util.h>
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#include "xe_force_wake.h"
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#include "xe_gt.h"
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#include "xe_mmio.h"
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#include "gt/intel_gt_regs.h"
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#define XE_FORCE_WAKE_ACK_TIMEOUT_MS 50
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static struct xe_gt *
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fw_to_gt(struct xe_force_wake *fw)
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{
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return fw->gt;
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}
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static struct xe_device *
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fw_to_xe(struct xe_force_wake *fw)
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{
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return gt_to_xe(fw_to_gt(fw));
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}
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static void domain_init(struct xe_force_wake_domain *domain,
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enum xe_force_wake_domain_id id,
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u32 reg, u32 ack, u32 val, u32 mask)
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{
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domain->id = id;
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domain->reg_ctl = reg;
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domain->reg_ack = ack;
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domain->val = val;
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domain->mask = mask;
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}
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#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
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void xe_force_wake_init_gt(struct xe_gt *gt, struct xe_force_wake *fw)
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{
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struct xe_device *xe = gt_to_xe(gt);
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fw->gt = gt;
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mutex_init(&fw->lock);
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/* Assuming gen11+ so assert this assumption is correct */
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XE_BUG_ON(GRAPHICS_VER(gt_to_xe(gt)) < 11);
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if (xe->info.platform == XE_METEORLAKE) {
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domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
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XE_FW_DOMAIN_ID_GT,
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FORCEWAKE_GT_GEN9.reg,
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FORCEWAKE_ACK_GT_MTL.reg,
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BIT(0), BIT(16));
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} else {
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domain_init(&fw->domains[XE_FW_DOMAIN_ID_GT],
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XE_FW_DOMAIN_ID_GT,
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FORCEWAKE_GT_GEN9.reg,
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FORCEWAKE_ACK_GT_GEN9.reg,
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BIT(0), BIT(16));
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}
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}
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void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
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{
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int i, j;
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/* Assuming gen11+ so assert this assumption is correct */
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XE_BUG_ON(GRAPHICS_VER(gt_to_xe(gt)) < 11);
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if (!xe_gt_is_media_type(gt))
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domain_init(&fw->domains[XE_FW_DOMAIN_ID_RENDER],
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XE_FW_DOMAIN_ID_RENDER,
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FORCEWAKE_RENDER_GEN9.reg,
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FORCEWAKE_ACK_RENDER_GEN9.reg,
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BIT(0), BIT(16));
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for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) {
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if (!(gt->info.engine_mask & BIT(i)))
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continue;
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domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j],
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XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j,
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FORCEWAKE_MEDIA_VDBOX_GEN11(j).reg,
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FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(j).reg,
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BIT(0), BIT(16));
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}
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for (i = XE_HW_ENGINE_VECS0, j =0; i <= XE_HW_ENGINE_VECS3; ++i, ++j) {
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if (!(gt->info.engine_mask & BIT(i)))
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continue;
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domain_init(&fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j],
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XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j,
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FORCEWAKE_MEDIA_VEBOX_GEN11(j).reg,
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FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(j).reg,
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BIT(0), BIT(16));
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}
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}
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void xe_force_wake_prune(struct xe_gt *gt, struct xe_force_wake *fw)
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{
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int i, j;
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/* Call after fuses have been read, prune domains that are fused off */
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for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j)
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if (!(gt->info.engine_mask & BIT(i)))
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fw->domains[XE_FW_DOMAIN_ID_MEDIA_VDBOX0 + j].reg_ctl = 0;
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for (i = XE_HW_ENGINE_VECS0, j =0; i <= XE_HW_ENGINE_VECS3; ++i, ++j)
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if (!(gt->info.engine_mask & BIT(i)))
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fw->domains[XE_FW_DOMAIN_ID_MEDIA_VEBOX0 + j].reg_ctl = 0;
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}
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static void domain_wake(struct xe_gt *gt, struct xe_force_wake_domain *domain)
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{
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xe_mmio_write32(gt, domain->reg_ctl, domain->mask | domain->val);
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}
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static int domain_wake_wait(struct xe_gt *gt,
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struct xe_force_wake_domain *domain)
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{
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return xe_mmio_wait32(gt, domain->reg_ack, domain->val, domain->val,
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XE_FORCE_WAKE_ACK_TIMEOUT_MS);
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}
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static void domain_sleep(struct xe_gt *gt, struct xe_force_wake_domain *domain)
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{
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xe_mmio_write32(gt, domain->reg_ctl, domain->mask);
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}
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static int domain_sleep_wait(struct xe_gt *gt,
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struct xe_force_wake_domain *domain)
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{
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return xe_mmio_wait32(gt, domain->reg_ack, 0, domain->val,
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XE_FORCE_WAKE_ACK_TIMEOUT_MS);
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}
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#define for_each_fw_domain_masked(domain__, mask__, fw__, tmp__) \
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for (tmp__ = (mask__); tmp__ ;) \
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for_each_if((domain__ = ((fw__)->domains + \
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__mask_next_bit(tmp__))) && \
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domain__->reg_ctl)
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int xe_force_wake_get(struct xe_force_wake *fw,
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enum xe_force_wake_domains domains)
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{
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struct xe_device *xe = fw_to_xe(fw);
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struct xe_gt *gt = fw_to_gt(fw);
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struct xe_force_wake_domain *domain;
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enum xe_force_wake_domains tmp, woken = 0;
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int ret, ret2 = 0;
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mutex_lock(&fw->lock);
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for_each_fw_domain_masked(domain, domains, fw, tmp) {
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if (!domain->ref++) {
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woken |= BIT(domain->id);
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domain_wake(gt, domain);
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}
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}
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for_each_fw_domain_masked(domain, woken, fw, tmp) {
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ret = domain_wake_wait(gt, domain);
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ret2 |= ret;
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if (ret)
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drm_notice(&xe->drm, "Force wake domain (%d) failed to ack wake, ret=%d\n",
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domain->id, ret);
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}
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fw->awake_domains |= woken;
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mutex_unlock(&fw->lock);
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return ret2;
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}
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int xe_force_wake_put(struct xe_force_wake *fw,
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enum xe_force_wake_domains domains)
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{
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struct xe_device *xe = fw_to_xe(fw);
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struct xe_gt *gt = fw_to_gt(fw);
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struct xe_force_wake_domain *domain;
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enum xe_force_wake_domains tmp, sleep = 0;
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int ret, ret2 = 0;
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mutex_lock(&fw->lock);
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for_each_fw_domain_masked(domain, domains, fw, tmp) {
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if (!--domain->ref) {
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sleep |= BIT(domain->id);
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domain_sleep(gt, domain);
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}
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}
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for_each_fw_domain_masked(domain, sleep, fw, tmp) {
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ret = domain_sleep_wait(gt, domain);
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ret2 |= ret;
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if (ret)
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drm_notice(&xe->drm, "Force wake domain (%d) failed to ack sleep, ret=%d\n",
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domain->id, ret);
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}
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fw->awake_domains &= ~sleep;
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mutex_unlock(&fw->lock);
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return ret2;
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}
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