84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "i915_reg.h"
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#include "gt/intel_gt_regs.h"
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_gt_clock.h"
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#include "xe_macros.h"
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#include "xe_mmio.h"
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static u32 read_reference_ts_freq(struct xe_gt *gt)
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{
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u32 ts_override = xe_mmio_read32(gt, GEN9_TIMESTAMP_OVERRIDE.reg);
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u32 base_freq, frac_freq;
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base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
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GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
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base_freq *= 1000000;
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frac_freq = ((ts_override &
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GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
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GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
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frac_freq = 1000000 / (frac_freq + 1);
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return base_freq + frac_freq;
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}
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static u32 get_crystal_clock_freq(u32 rpm_config_reg)
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{
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const u32 f19_2_mhz = 19200000;
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const u32 f24_mhz = 24000000;
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const u32 f25_mhz = 25000000;
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const u32 f38_4_mhz = 38400000;
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u32 crystal_clock =
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(rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
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GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
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switch (crystal_clock) {
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
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return f24_mhz;
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
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return f19_2_mhz;
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
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return f38_4_mhz;
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case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
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return f25_mhz;
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default:
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XE_BUG_ON("NOT_POSSIBLE");
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return 0;
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}
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}
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int xe_gt_clock_init(struct xe_gt *gt)
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{
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u32 ctc_reg = xe_mmio_read32(gt, CTC_MODE.reg);
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u32 freq = 0;
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/* Assuming gen11+ so assert this assumption is correct */
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XE_BUG_ON(GRAPHICS_VER(gt_to_xe(gt)) < 11);
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if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
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freq = read_reference_ts_freq(gt);
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} else {
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u32 c0 = xe_mmio_read32(gt, RPM_CONFIG0.reg);
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freq = get_crystal_clock_freq(c0);
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/*
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* Now figure out how the command stream's timestamp
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* register increments from this frequency (it might
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* increment only every few clock cycle).
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*/
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freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
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GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
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}
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gt->info.clock_freq = freq;
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return 0;
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}
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