553 lines
17 KiB
C
553 lines
17 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_gt.h"
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#include "xe_gt_mcr.h"
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#include "xe_gt_topology.h"
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#include "xe_gt_types.h"
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#include "xe_mmio.h"
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#include "gt/intel_gt_regs.h"
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/**
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* DOC: GT Multicast/Replicated (MCR) Register Support
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*
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* Some GT registers are designed as "multicast" or "replicated" registers:
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* multiple instances of the same register share a single MMIO offset. MCR
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* registers are generally used when the hardware needs to potentially track
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* independent values of a register per hardware unit (e.g., per-subslice,
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* per-L3bank, etc.). The specific types of replication that exist vary
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* per-platform.
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*
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* MMIO accesses to MCR registers are controlled according to the settings
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* programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR
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* registers can be done in either a (i.e., a single write updates all
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* instances of the register to the same value) or unicast (a write updates only
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* one specific instance). Reads of MCR registers always operate in a unicast
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* manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR.
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* Selection of a specific MCR instance for unicast operations is referred to
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* as "steering."
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*
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* If MCR register operations are steered toward a hardware unit that is
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* fused off or currently powered down due to power gating, the MMIO operation
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* is "terminated" by the hardware. Terminated read operations will return a
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* value of zero and terminated unicast write operations will be silently
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* ignored.
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*/
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enum {
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MCR_OP_READ,
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MCR_OP_WRITE
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};
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static const struct xe_mmio_range xelp_l3bank_steering_table[] = {
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{ 0x00B100, 0x00B3FF },
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{},
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};
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/*
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* Although the bspec lists more "MSLICE" ranges than shown here, some of those
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* are of a "GAM" subclass that has special rules and doesn't need to be
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* included here.
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*/
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static const struct xe_mmio_range xehp_mslice_steering_table[] = {
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{ 0x00DD00, 0x00DDFF },
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{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
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{},
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};
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static const struct xe_mmio_range xehp_lncf_steering_table[] = {
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{ 0x00B000, 0x00B0FF },
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{ 0x00D880, 0x00D8FF },
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{},
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};
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/*
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* We have several types of MCR registers where steering to (0,0) will always
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* provide us with a non-terminated value. We'll stick them all in the same
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* table for simplicity.
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*/
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static const struct xe_mmio_range xehpc_instance0_steering_table[] = {
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{ 0x004000, 0x004AFF }, /* HALF-BSLICE */
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{ 0x008800, 0x00887F }, /* CC */
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{ 0x008A80, 0x008AFF }, /* TILEPSMI */
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{ 0x00B000, 0x00B0FF }, /* HALF-BSLICE */
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{ 0x00B100, 0x00B3FF }, /* L3BANK */
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{ 0x00C800, 0x00CFFF }, /* HALF-BSLICE */
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{ 0x00D800, 0x00D8FF }, /* HALF-BSLICE */
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{ 0x00DD00, 0x00DDFF }, /* BSLICE */
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{ 0x00E900, 0x00E9FF }, /* HALF-BSLICE */
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{ 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */
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{ 0x00F000, 0x00FFFF }, /* HALF-BSLICE */
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{ 0x024180, 0x0241FF }, /* HALF-BSLICE */
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{},
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};
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static const struct xe_mmio_range xelpg_instance0_steering_table[] = {
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{ 0x000B00, 0x000BFF }, /* SQIDI */
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{ 0x001000, 0x001FFF }, /* SQIDI */
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{ 0x004000, 0x0048FF }, /* GAM */
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{ 0x008700, 0x0087FF }, /* SQIDI */
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{ 0x00B000, 0x00B0FF }, /* NODE */
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{ 0x00C800, 0x00CFFF }, /* GAM */
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{ 0x00D880, 0x00D8FF }, /* NODE */
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{ 0x00DD00, 0x00DDFF }, /* OAAL2 */
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{},
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};
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static const struct xe_mmio_range xelpg_l3bank_steering_table[] = {
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{ 0x00B100, 0x00B3FF },
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{},
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};
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static const struct xe_mmio_range xelp_dss_steering_table[] = {
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{ 0x008150, 0x00815F },
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{ 0x009520, 0x00955F },
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{ 0x00DE80, 0x00E8FF },
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{ 0x024A00, 0x024A7F },
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{},
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};
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/* DSS steering is used for GSLICE ranges as well */
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static const struct xe_mmio_range xehp_dss_steering_table[] = {
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{ 0x005200, 0x0052FF }, /* GSLICE */
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{ 0x005400, 0x007FFF }, /* GSLICE */
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{ 0x008140, 0x00815F }, /* GSLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
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{ 0x008D00, 0x008DFF }, /* DSS */
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{ 0x0094D0, 0x00955F }, /* GSLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
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{ 0x009680, 0x0096FF }, /* DSS */
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{ 0x00D800, 0x00D87F }, /* GSLICE */
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{ 0x00DC00, 0x00DCFF }, /* GSLICE */
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{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved ) */
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{ 0x017000, 0x017FFF }, /* GSLICE */
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{ 0x024A00, 0x024A7F }, /* DSS */
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{},
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};
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/* DSS steering is used for COMPUTE ranges as well */
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static const struct xe_mmio_range xehpc_dss_steering_table[] = {
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{ 0x008140, 0x00817F }, /* COMPUTE (0x8140-0x814F & 0x8160-0x817F), DSS (0x8150-0x815F) */
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{ 0x0094D0, 0x00955F }, /* COMPUTE (0x94D0-0x951F), DSS (0x9520-0x955F) */
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{ 0x009680, 0x0096FF }, /* DSS */
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{ 0x00DC00, 0x00DCFF }, /* COMPUTE */
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{ 0x00DE80, 0x00E7FF }, /* DSS (0xDF00-0xE1FF reserved ) */
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{},
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};
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/* DSS steering is used for SLICE ranges as well */
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static const struct xe_mmio_range xelpg_dss_steering_table[] = {
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{ 0x005200, 0x0052FF }, /* SLICE */
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{ 0x005500, 0x007FFF }, /* SLICE */
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{ 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
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{ 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
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{ 0x009680, 0x0096FF }, /* DSS */
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{ 0x00D800, 0x00D87F }, /* SLICE */
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{ 0x00DC00, 0x00DCFF }, /* SLICE */
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{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
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{},
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};
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static const struct xe_mmio_range xelpmp_oaddrm_steering_table[] = {
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{ 0x393200, 0x39323F },
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{ 0x393400, 0x3934FF },
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{},
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};
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/*
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* DG2 GAM registers are a special case; this table is checked directly in
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* xe_gt_mcr_get_nonterminated_steering and is not hooked up via
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* gt->steering[].
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*/
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static const struct xe_mmio_range dg2_gam_ranges[] = {
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{ 0x004000, 0x004AFF },
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{ 0x00C800, 0x00CFFF },
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{ 0x00F000, 0x00FFFF },
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{},
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};
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static void init_steering_l3bank(struct xe_gt *gt)
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{
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if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
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u32 mslice_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK,
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xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
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u32 bank_mask = REG_FIELD_GET(GT_L3_EXC_MASK,
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xe_mmio_read32(gt, XEHP_FUSE4.reg));
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/*
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* Group selects mslice, instance selects bank within mslice.
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* Bank 0 is always valid _except_ when the bank mask is 010b.
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*/
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gt->steering[L3BANK].group_target = __ffs(mslice_mask);
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gt->steering[L3BANK].instance_target =
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bank_mask & BIT(0) ? 0 : 2;
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} else {
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u32 fuse = REG_FIELD_GET(GEN10_L3BANK_MASK,
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~xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
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gt->steering[L3BANK].group_target = 0; /* unused */
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gt->steering[L3BANK].instance_target = __ffs(fuse);
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}
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}
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static void init_steering_mslice(struct xe_gt *gt)
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{
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u32 mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK,
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xe_mmio_read32(gt, GEN10_MIRROR_FUSE3.reg));
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/*
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* mslice registers are valid (not terminated) if either the meml3
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* associated with the mslice is present, or at least one DSS associated
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* with the mslice is present. There will always be at least one meml3
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* so we can just use that to find a non-terminated mslice and ignore
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* the DSS fusing.
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*/
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gt->steering[MSLICE].group_target = __ffs(mask);
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gt->steering[MSLICE].instance_target = 0; /* unused */
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/*
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* LNCF termination is also based on mslice presence, so we'll set
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* it up here. Either LNCF within a non-terminated mslice will work,
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* so we just always pick LNCF 0 here.
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*/
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gt->steering[LNCF].group_target = __ffs(mask) << 1;
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gt->steering[LNCF].instance_target = 0; /* unused */
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}
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static void init_steering_dss(struct xe_gt *gt)
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{
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unsigned int dss = min(xe_dss_mask_group_ffs(gt->fuse_topo.g_dss_mask, 0, 0),
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xe_dss_mask_group_ffs(gt->fuse_topo.c_dss_mask, 0, 0));
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unsigned int dss_per_grp = gt_to_xe(gt)->info.platform == XE_PVC ? 8 : 4;
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gt->steering[DSS].group_target = dss / dss_per_grp;
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gt->steering[DSS].instance_target = dss % dss_per_grp;
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}
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static void init_steering_oaddrm(struct xe_gt *gt)
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{
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/*
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* First instance is only terminated if the entire first media slice
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* is absent (i.e., no VCS0 or VECS0).
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*/
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if (gt->info.engine_mask & (XE_HW_ENGINE_VCS0 | XE_HW_ENGINE_VECS0))
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gt->steering[OADDRM].group_target = 0;
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else
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gt->steering[OADDRM].group_target = 1;
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gt->steering[DSS].instance_target = 0; /* unused */
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}
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static void init_steering_inst0(struct xe_gt *gt)
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{
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gt->steering[DSS].group_target = 0; /* unused */
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gt->steering[DSS].instance_target = 0; /* unused */
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}
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static const struct {
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const char *name;
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void (*init)(struct xe_gt *);
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} xe_steering_types[] = {
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{ "L3BANK", init_steering_l3bank },
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{ "MSLICE", init_steering_mslice },
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{ "LNCF", NULL }, /* initialized by mslice init */
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{ "DSS", init_steering_dss },
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{ "OADDRM", init_steering_oaddrm },
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{ "INSTANCE 0", init_steering_inst0 },
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};
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void xe_gt_mcr_init(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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BUILD_BUG_ON(ARRAY_SIZE(xe_steering_types) != NUM_STEERING_TYPES);
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spin_lock_init(>->mcr_lock);
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if (gt->info.type == XE_GT_TYPE_MEDIA) {
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drm_WARN_ON(&xe->drm, MEDIA_VER(xe) < 13);
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gt->steering[OADDRM].ranges = xelpmp_oaddrm_steering_table;
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} else if (GRAPHICS_VERx100(xe) >= 1270) {
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gt->steering[INSTANCE0].ranges = xelpg_instance0_steering_table;
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gt->steering[L3BANK].ranges = xelpg_l3bank_steering_table;
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gt->steering[DSS].ranges = xelpg_dss_steering_table;
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} else if (xe->info.platform == XE_PVC) {
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gt->steering[INSTANCE0].ranges = xehpc_instance0_steering_table;
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gt->steering[DSS].ranges = xehpc_dss_steering_table;
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} else if (xe->info.platform == XE_DG2) {
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gt->steering[MSLICE].ranges = xehp_mslice_steering_table;
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gt->steering[LNCF].ranges = xehp_lncf_steering_table;
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gt->steering[DSS].ranges = xehp_dss_steering_table;
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} else {
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gt->steering[L3BANK].ranges = xelp_l3bank_steering_table;
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gt->steering[DSS].ranges = xelp_dss_steering_table;
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}
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/* Select non-terminated steering target for each type */
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for (int i = 0; i < NUM_STEERING_TYPES; i++)
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if (gt->steering[i].ranges && xe_steering_types[i].init)
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xe_steering_types[i].init(gt);
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}
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/*
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* xe_gt_mcr_get_nonterminated_steering - find group/instance values that
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* will steer a register to a non-terminated instance
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* @gt: GT structure
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* @reg: register for which the steering is required
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* @group: return variable for group steering
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* @instance: return variable for instance steering
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*
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* This function returns a group/instance pair that is guaranteed to work for
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* read steering of the given register. Note that a value will be returned even
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* if the register is not replicated and therefore does not actually require
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* steering.
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*
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* Returns true if the caller should steer to the @group/@instance values
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* returned. Returns false if the caller need not perform any steering (i.e.,
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* the DG2 GAM range special case).
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*/
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static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
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i915_mcr_reg_t reg,
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u8 *group, u8 *instance)
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{
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for (int type = 0; type < NUM_STEERING_TYPES; type++) {
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if (!gt->steering[type].ranges)
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continue;
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for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {
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if (xe_mmio_in_range(>->steering[type].ranges[i], reg.reg)) {
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*group = gt->steering[type].group_target;
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*instance = gt->steering[type].instance_target;
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return true;
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}
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}
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}
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/*
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* All MCR registers should usually be part of one of the steering
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* ranges we're tracking. However there's one special case: DG2
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* GAM registers are technically multicast registers, but are special
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* in a number of ways:
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* - they have their own dedicated steering control register (they
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* don't share 0xFDC with other MCR classes)
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* - all reads should be directed to instance 1 (unicast reads against
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* other instances are not allowed), and instance 1 is already the
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* the hardware's default steering target, which we never change
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*
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* Ultimately this means that we can just treat them as if they were
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* unicast registers and all operations will work properly.
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*/
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for (int i = 0; dg2_gam_ranges[i].end > 0; i++)
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if (xe_mmio_in_range(&dg2_gam_ranges[i], reg.reg))
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return false;
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/*
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* Not found in a steering table and not a DG2 GAM register? We'll
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* just steer to 0/0 as a guess and raise a warning.
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*/
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drm_WARN(>_to_xe(gt)->drm, true,
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"Did not find MCR register %#x in any MCR steering table\n",
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reg.reg);
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*group = 0;
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*instance = 0;
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return true;
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}
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#define STEER_SEMAPHORE 0xFD0
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/*
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* Obtain exclusive access to MCR steering. On MTL and beyond we also need
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* to synchronize with external clients (e.g., firmware), so a semaphore
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* register will also need to be taken.
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*/
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static void mcr_lock(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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int ret;
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spin_lock(>->mcr_lock);
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/*
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* Starting with MTL we also need to grab a semaphore register
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* to synchronize with external agents (e.g., firmware) that now
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* shares the same steering control register.
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*/
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if (GRAPHICS_VERx100(xe) >= 1270)
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ret = wait_for_us(xe_mmio_read32(gt, STEER_SEMAPHORE) == 0x1, 10);
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drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
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}
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static void mcr_unlock(struct xe_gt *gt) {
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/* Release hardware semaphore */
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if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
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xe_mmio_write32(gt, STEER_SEMAPHORE, 0x1);
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spin_unlock(>->mcr_lock);
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}
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/*
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* Access a register with specific MCR steering
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*
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* Caller needs to make sure the relevant forcewake wells are up.
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*/
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static u32 rw_with_mcr_steering(struct xe_gt *gt, i915_mcr_reg_t reg, u8 rw_flag,
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int group, int instance, u32 value)
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{
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u32 steer_reg, steer_val, val = 0;
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lockdep_assert_held(>->mcr_lock);
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if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) {
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steer_reg = MTL_MCR_SELECTOR.reg;
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steer_val = REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
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REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance);
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} else {
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steer_reg = GEN8_MCR_SELECTOR.reg;
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steer_val = REG_FIELD_PREP(GEN11_MCR_SLICE_MASK, group) |
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REG_FIELD_PREP(GEN11_MCR_SUBSLICE_MASK, instance);
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}
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/*
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* Always leave the hardware in multicast mode when doing reads
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* (see comment about Wa_22013088509 below) and only change it
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* to unicast mode when doing writes of a specific instance.
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*
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* No need to save old steering reg value.
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*/
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if (rw_flag == MCR_OP_READ)
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steer_val |= GEN11_MCR_MULTICAST;
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xe_mmio_write32(gt, steer_reg, steer_val);
|
|
|
|
if (rw_flag == MCR_OP_READ)
|
|
val = xe_mmio_read32(gt, reg.reg);
|
|
else
|
|
xe_mmio_write32(gt, reg.reg, value);
|
|
|
|
/*
|
|
* If we turned off the multicast bit (during a write) we're required
|
|
* to turn it back on before finishing. The group and instance values
|
|
* don't matter since they'll be re-programmed on the next MCR
|
|
* operation.
|
|
*/
|
|
if (rw_flag == MCR_OP_WRITE)
|
|
xe_mmio_write32(gt, steer_reg, GEN11_MCR_MULTICAST);
|
|
|
|
return val;
|
|
}
|
|
|
|
/**
|
|
* xe_gt_mcr_unicast_read_any - reads a non-terminated instance of an MCR register
|
|
* @gt: GT structure
|
|
* @reg: register to read
|
|
*
|
|
* Reads a GT MCR register. The read will be steered to a non-terminated
|
|
* instance (i.e., one that isn't fused off or powered down by power gating).
|
|
* This function assumes the caller is already holding any necessary forcewake
|
|
* domains.
|
|
*
|
|
* Returns the value from a non-terminated instance of @reg.
|
|
*/
|
|
u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, i915_mcr_reg_t reg)
|
|
{
|
|
u8 group, instance;
|
|
u32 val;
|
|
bool steer;
|
|
|
|
steer = xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance);
|
|
|
|
if (steer) {
|
|
mcr_lock(gt);
|
|
val = rw_with_mcr_steering(gt, reg, MCR_OP_READ,
|
|
group, instance, 0);
|
|
mcr_unlock(gt);
|
|
} else {
|
|
/* DG2 GAM special case rules; treat as if unicast */
|
|
val = xe_mmio_read32(gt, reg.reg);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
/**
|
|
* xe_gt_mcr_unicast_read - read a specific instance of an MCR register
|
|
* @gt: GT structure
|
|
* @reg: the MCR register to read
|
|
* @group: the MCR group
|
|
* @instance: the MCR instance
|
|
*
|
|
* Returns the value read from an MCR register after steering toward a specific
|
|
* group/instance.
|
|
*/
|
|
u32 xe_gt_mcr_unicast_read(struct xe_gt *gt,
|
|
i915_mcr_reg_t reg,
|
|
int group, int instance)
|
|
{
|
|
u32 val;
|
|
|
|
mcr_lock(gt);
|
|
val = rw_with_mcr_steering(gt, reg, MCR_OP_READ, group, instance, 0);
|
|
mcr_unlock(gt);
|
|
|
|
return val;
|
|
}
|
|
|
|
/**
|
|
* xe_gt_mcr_unicast_write - write a specific instance of an MCR register
|
|
* @gt: GT structure
|
|
* @reg: the MCR register to write
|
|
* @value: value to write
|
|
* @group: the MCR group
|
|
* @instance: the MCR instance
|
|
*
|
|
* Write an MCR register in unicast mode after steering toward a specific
|
|
* group/instance.
|
|
*/
|
|
void xe_gt_mcr_unicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value,
|
|
int group, int instance)
|
|
{
|
|
mcr_lock(gt);
|
|
rw_with_mcr_steering(gt, reg, MCR_OP_WRITE, group, instance, value);
|
|
mcr_unlock(gt);
|
|
}
|
|
|
|
/**
|
|
* xe_gt_mcr_multicast_write - write a value to all instances of an MCR register
|
|
* @gt: GT structure
|
|
* @reg: the MCR register to write
|
|
* @value: value to write
|
|
*
|
|
* Write an MCR register in multicast mode to update all instances.
|
|
*/
|
|
void xe_gt_mcr_multicast_write(struct xe_gt *gt, i915_mcr_reg_t reg, u32 value)
|
|
{
|
|
/*
|
|
* Synchronize with any unicast operations. Once we have exclusive
|
|
* access, the MULTICAST bit should already be set, so there's no need
|
|
* to touch the steering register.
|
|
*/
|
|
mcr_lock(gt);
|
|
xe_mmio_write32(gt, reg.reg, value);
|
|
mcr_unlock(gt);
|
|
}
|
|
|
|
void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p)
|
|
{
|
|
for (int i = 0; i < NUM_STEERING_TYPES; i++) {
|
|
if (gt->steering[i].ranges) {
|
|
drm_printf(p, "%s steering: group=%#x, instance=%#x\n",
|
|
xe_steering_types[i].name,
|
|
gt->steering[i].group_target,
|
|
gt->steering[i].instance_target);
|
|
for (int j = 0; gt->steering[i].ranges[j].end; j++)
|
|
drm_printf(p, "\t0x%06x - 0x%06x\n",
|
|
gt->steering[i].ranges[j].start,
|
|
gt->steering[i].ranges[j].end);
|
|
}
|
|
}
|
|
}
|