145 lines
3.6 KiB
C
145 lines
3.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <linux/bitmap.h>
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#include "xe_gt.h"
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#include "xe_gt_topology.h"
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#include "xe_mmio.h"
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#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
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#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)
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#define XELP_EU_ENABLE 0x9134 /* "_DISABLE" on Xe_LP */
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#define XELP_EU_MASK REG_GENMASK(7, 0)
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#define XELP_GT_GEOMETRY_DSS_ENABLE 0x913c
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#define XEHP_GT_COMPUTE_DSS_ENABLE 0x9144
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#define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT 0x9148
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static void
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load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
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{
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va_list argp;
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u32 fuse_val[XE_MAX_DSS_FUSE_REGS] = {};
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int i;
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if (drm_WARN_ON(>_to_xe(gt)->drm, numregs > XE_MAX_DSS_FUSE_REGS))
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numregs = XE_MAX_DSS_FUSE_REGS;
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va_start(argp, numregs);
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for (i = 0; i < numregs; i++)
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fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, u32));
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va_end(argp);
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bitmap_from_arr32(mask, fuse_val, numregs * 32);
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}
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static void
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load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask)
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{
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struct xe_device *xe = gt_to_xe(gt);
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u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE);
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u32 val = 0;
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int i;
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BUILD_BUG_ON(XE_MAX_EU_FUSE_REGS > 1);
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/*
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* Pre-Xe_HP platforms inverted the bit meaning (disable instead
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* of enable).
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*/
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if (GRAPHICS_VERx100(xe) < 1250)
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reg = ~reg & XELP_EU_MASK;
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/* On PVC, one bit = one EU */
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if (GRAPHICS_VERx100(xe) == 1260) {
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val = reg;
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} else {
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/* All other platforms, one bit = 2 EU */
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for (i = 0; i < fls(reg); i++)
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if (reg & BIT(i))
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val |= 0x3 << 2 * i;
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}
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bitmap_from_arr32(mask, &val, XE_MAX_EU_FUSE_BITS);
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}
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void
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xe_gt_topology_init(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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struct drm_printer p = drm_debug_printer("GT topology");
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int num_geometry_regs, num_compute_regs;
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if (GRAPHICS_VERx100(xe) == 1260) {
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num_geometry_regs = 0;
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num_compute_regs = 2;
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} else if (GRAPHICS_VERx100(xe) >= 1250) {
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num_geometry_regs = 1;
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num_compute_regs = 1;
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} else {
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num_geometry_regs = 1;
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num_compute_regs = 0;
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}
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load_dss_mask(gt, gt->fuse_topo.g_dss_mask, num_geometry_regs,
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XELP_GT_GEOMETRY_DSS_ENABLE);
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load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs,
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XEHP_GT_COMPUTE_DSS_ENABLE,
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XEHPC_GT_COMPUTE_DSS_ENABLE_EXT);
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load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss);
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xe_gt_topology_dump(gt, &p);
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}
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unsigned int
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xe_gt_topology_count_dss(xe_dss_mask_t mask)
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{
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return bitmap_weight(mask, XE_MAX_DSS_FUSE_BITS);
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}
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u64
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xe_gt_topology_dss_group_mask(xe_dss_mask_t mask, int grpsize)
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{
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xe_dss_mask_t per_dss_mask = {};
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u64 grpmask = 0;
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WARN_ON(DIV_ROUND_UP(XE_MAX_DSS_FUSE_BITS, grpsize) > BITS_PER_TYPE(grpmask));
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bitmap_fill(per_dss_mask, grpsize);
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for (int i = 0; !bitmap_empty(mask, XE_MAX_DSS_FUSE_BITS); i++) {
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if (bitmap_intersects(mask, per_dss_mask, grpsize))
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grpmask |= BIT(i);
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bitmap_shift_right(mask, mask, grpsize, XE_MAX_DSS_FUSE_BITS);
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}
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return grpmask;
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}
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void
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xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p)
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{
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drm_printf(p, "dss mask (geometry): %*pb\n", XE_MAX_DSS_FUSE_BITS,
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gt->fuse_topo.g_dss_mask);
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drm_printf(p, "dss mask (compute): %*pb\n", XE_MAX_DSS_FUSE_BITS,
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gt->fuse_topo.c_dss_mask);
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drm_printf(p, "EU mask per DSS: %*pb\n", XE_MAX_EU_FUSE_BITS,
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gt->fuse_topo.eu_mask_per_dss);
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}
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/*
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* Used to obtain the index of the first DSS. Can start searching from the
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* beginning of a specific dss group (e.g., gslice, cslice, etc.) if
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* groupsize and groupnum are non-zero.
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*/
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unsigned int
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xe_dss_mask_group_ffs(xe_dss_mask_t mask, int groupsize, int groupnum)
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{
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return find_next_bit(mask, XE_MAX_DSS_FUSE_BITS, groupnum * groupsize);
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}
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