677 lines
19 KiB
C
677 lines
19 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <drm/drm_managed.h>
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#include "xe_bo.h"
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#include "xe_gt.h"
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#include "xe_guc.h"
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#include "xe_guc_ads.h"
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#include "xe_guc_reg.h"
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#include "xe_hw_engine.h"
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#include "xe_lrc.h"
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#include "xe_map.h"
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#include "xe_mmio.h"
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#include "xe_platform_types.h"
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#include "gt/intel_gt_regs.h"
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#include "gt/intel_engine_regs.h"
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/* Slack of a few additional entries per engine */
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#define ADS_REGSET_EXTRA_MAX 8
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static struct xe_guc *
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ads_to_guc(struct xe_guc_ads *ads)
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{
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return container_of(ads, struct xe_guc, ads);
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}
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static struct xe_gt *
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ads_to_gt(struct xe_guc_ads *ads)
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{
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return container_of(ads, struct xe_gt, uc.guc.ads);
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}
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static struct xe_device *
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ads_to_xe(struct xe_guc_ads *ads)
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{
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return gt_to_xe(ads_to_gt(ads));
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}
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static struct iosys_map *
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ads_to_map(struct xe_guc_ads *ads)
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{
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return &ads->bo->vmap;
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}
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/* UM Queue parameters: */
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#define GUC_UM_QUEUE_SIZE (SZ_64K)
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#define GUC_PAGE_RES_TIMEOUT_US (-1)
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/*
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* The Additional Data Struct (ADS) has pointers for different buffers used by
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* the GuC. One single gem object contains the ADS struct itself (guc_ads) and
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* all the extra buffers indirectly linked via the ADS struct's entries.
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*
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* Layout of the ADS blob allocated for the GuC:
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*
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* +---------------------------------------+ <== base
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* | guc_ads |
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* +---------------------------------------+
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* | guc_policies |
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* +---------------------------------------+
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* | guc_gt_system_info |
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* +---------------------------------------+
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* | guc_engine_usage |
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* +---------------------------------------+
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* | guc_um_init_params |
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* +---------------------------------------+ <== static
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* | guc_mmio_reg[countA] (engine 0.0) |
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* | guc_mmio_reg[countB] (engine 0.1) |
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* | guc_mmio_reg[countC] (engine 1.0) |
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* | ... |
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* +---------------------------------------+ <== dynamic
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* | padding |
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* +---------------------------------------+ <== 4K aligned
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* | golden contexts |
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* +---------------------------------------+
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* | padding |
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* +---------------------------------------+ <== 4K aligned
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* | capture lists |
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* +---------------------------------------+
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* | padding |
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* +---------------------------------------+ <== 4K aligned
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* | UM queues |
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* +---------------------------------------+
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* | padding |
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* +---------------------------------------+ <== 4K aligned
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* | private data |
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* +---------------------------------------+
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* | padding |
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* +---------------------------------------+ <== 4K aligned
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*/
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struct __guc_ads_blob {
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struct guc_ads ads;
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struct guc_policies policies;
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struct guc_gt_system_info system_info;
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struct guc_engine_usage engine_usage;
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struct guc_um_init_params um_init_params;
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/* From here on, location is dynamic! Refer to above diagram. */
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struct guc_mmio_reg regset[0];
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} __packed;
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#define ads_blob_read(ads_, field_) \
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xe_map_rd_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \
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struct __guc_ads_blob, field_)
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#define ads_blob_write(ads_, field_, val_) \
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xe_map_wr_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \
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struct __guc_ads_blob, field_, val_)
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#define info_map_write(xe_, map_, field_, val_) \
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xe_map_wr_field(xe_, map_, 0, struct guc_gt_system_info, field_, val_)
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#define info_map_read(xe_, map_, field_) \
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xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_)
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static size_t guc_ads_regset_size(struct xe_guc_ads *ads)
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{
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XE_BUG_ON(!ads->regset_size);
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return ads->regset_size;
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}
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static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads)
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{
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return PAGE_ALIGN(ads->golden_lrc_size);
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}
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static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
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{
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/* FIXME: Allocate a proper capture list */
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return PAGE_ALIGN(PAGE_SIZE);
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}
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static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads)
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{
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struct xe_device *xe = ads_to_xe(ads);
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if (!xe->info.supports_usm)
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return 0;
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return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX;
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}
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static size_t guc_ads_private_data_size(struct xe_guc_ads *ads)
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{
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return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size);
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}
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static size_t guc_ads_regset_offset(struct xe_guc_ads *ads)
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{
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return offsetof(struct __guc_ads_blob, regset);
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}
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static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads)
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{
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size_t offset;
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offset = guc_ads_regset_offset(ads) +
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guc_ads_regset_size(ads);
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return PAGE_ALIGN(offset);
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}
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static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
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{
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size_t offset;
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offset = guc_ads_golden_lrc_offset(ads) +
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guc_ads_golden_lrc_size(ads);
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return PAGE_ALIGN(offset);
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}
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static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads)
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{
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u32 offset;
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offset = guc_ads_capture_offset(ads) +
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guc_ads_capture_size(ads);
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return PAGE_ALIGN(offset);
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}
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static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads)
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{
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size_t offset;
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offset = guc_ads_um_queues_offset(ads) +
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guc_ads_um_queues_size(ads);
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return PAGE_ALIGN(offset);
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}
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static size_t guc_ads_size(struct xe_guc_ads *ads)
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{
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return guc_ads_private_data_offset(ads) +
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guc_ads_private_data_size(ads);
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}
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static void guc_ads_fini(struct drm_device *drm, void *arg)
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{
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struct xe_guc_ads *ads = arg;
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xe_bo_unpin_map_no_vm(ads->bo);
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}
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static size_t calculate_regset_size(struct xe_gt *gt)
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{
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struct xe_reg_sr_entry *sr_entry;
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unsigned long sr_idx;
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struct xe_hw_engine *hwe;
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enum xe_hw_engine_id id;
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unsigned int count = 0;
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for_each_hw_engine(hwe, gt, id)
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xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry)
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count++;
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count += (ADS_REGSET_EXTRA_MAX + LNCFCMOCS_REG_COUNT) * XE_NUM_HW_ENGINES;
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return count * sizeof(struct guc_mmio_reg);
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}
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static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class)
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{
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struct xe_hw_engine *hwe;
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enum xe_hw_engine_id id;
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u32 mask = 0;
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for_each_hw_engine(hwe, gt, id)
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if (hwe->class == class)
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mask |= BIT(hwe->instance);
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return mask;
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}
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static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
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{
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struct xe_device *xe = ads_to_xe(ads);
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struct xe_gt *gt = ads_to_gt(ads);
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size_t total_size = 0, alloc_size, real_size;
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int class;
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for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
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if (class == XE_ENGINE_CLASS_OTHER)
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continue;
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if (!engine_enable_mask(gt, class))
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continue;
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real_size = xe_lrc_size(xe, class);
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alloc_size = PAGE_ALIGN(real_size);
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total_size += alloc_size;
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}
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return total_size;
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}
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#define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64)
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int xe_guc_ads_init(struct xe_guc_ads *ads)
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{
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struct xe_device *xe = ads_to_xe(ads);
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struct xe_gt *gt = ads_to_gt(ads);
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struct xe_bo *bo;
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int err;
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ads->golden_lrc_size = calculate_golden_lrc_size(ads);
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ads->regset_size = calculate_regset_size(gt);
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bo = xe_bo_create_pin_map(xe, gt, NULL, guc_ads_size(ads) +
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MAX_GOLDEN_LRC_SIZE,
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ttm_bo_type_kernel,
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XE_BO_CREATE_VRAM_IF_DGFX(gt) |
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XE_BO_CREATE_GGTT_BIT);
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if (IS_ERR(bo))
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return PTR_ERR(bo);
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ads->bo = bo;
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err = drmm_add_action_or_reset(&xe->drm, guc_ads_fini, ads);
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if (err)
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return err;
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return 0;
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}
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/**
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* xe_guc_ads_init_post_hwconfig - initialize ADS post hwconfig load
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* @ads: Additional data structures object
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*
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* Recalcuate golden_lrc_size & regset_size as the number hardware engines may
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* have changed after the hwconfig was loaded. Also verify the new sizes fit in
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* the already allocated ADS buffer object.
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*
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* Return: 0 on success, negative error code on error.
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*/
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int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads)
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{
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struct xe_gt *gt = ads_to_gt(ads);
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u32 prev_regset_size = ads->regset_size;
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XE_BUG_ON(!ads->bo);
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ads->golden_lrc_size = calculate_golden_lrc_size(ads);
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ads->regset_size = calculate_regset_size(gt);
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XE_WARN_ON(ads->golden_lrc_size +
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(ads->regset_size - prev_regset_size) >
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MAX_GOLDEN_LRC_SIZE);
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return 0;
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}
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static void guc_policies_init(struct xe_guc_ads *ads)
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{
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ads_blob_write(ads, policies.dpc_promote_time,
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GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US);
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ads_blob_write(ads, policies.max_num_work_items,
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GLOBAL_POLICY_MAX_NUM_WI);
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ads_blob_write(ads, policies.global_flags, 0);
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ads_blob_write(ads, policies.is_valid, 1);
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}
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static void fill_engine_enable_masks(struct xe_gt *gt,
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struct iosys_map *info_map)
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{
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struct xe_device *xe = gt_to_xe(gt);
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info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS],
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engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER));
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info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS],
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engine_enable_mask(gt, XE_ENGINE_CLASS_COPY));
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info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
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engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE));
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info_map_write(xe, info_map,
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engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
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engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));
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info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],
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engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
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}
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static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads)
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{
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struct xe_device *xe = ads_to_xe(ads);
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struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
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offsetof(struct __guc_ads_blob, system_info));
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u8 guc_class;
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for (guc_class = 0; guc_class <= GUC_MAX_ENGINE_CLASSES; ++guc_class) {
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if (!info_map_read(xe, &info_map,
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engine_enabled_masks[guc_class]))
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continue;
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ads_blob_write(ads, ads.eng_state_size[guc_class],
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guc_ads_golden_lrc_size(ads) -
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xe_lrc_skip_size(xe));
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ads_blob_write(ads, ads.golden_context_lrca[guc_class],
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xe_bo_ggtt_addr(ads->bo) +
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guc_ads_golden_lrc_offset(ads));
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}
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}
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static void guc_mapping_table_init_invalid(struct xe_gt *gt,
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struct iosys_map *info_map)
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{
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struct xe_device *xe = gt_to_xe(gt);
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unsigned int i, j;
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/* Table must be set to invalid values for entries not used */
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for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)
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for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j)
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info_map_write(xe, info_map, mapping_table[i][j],
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GUC_MAX_INSTANCES_PER_CLASS);
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}
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static void guc_mapping_table_init(struct xe_gt *gt,
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struct iosys_map *info_map)
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{
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struct xe_device *xe = gt_to_xe(gt);
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struct xe_hw_engine *hwe;
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enum xe_hw_engine_id id;
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guc_mapping_table_init_invalid(gt, info_map);
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for_each_hw_engine(hwe, gt, id) {
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u8 guc_class;
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guc_class = xe_engine_class_to_guc_class(hwe->class);
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info_map_write(xe, info_map,
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mapping_table[guc_class][hwe->logical_instance],
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hwe->instance);
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}
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}
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static void guc_capture_list_init(struct xe_guc_ads *ads)
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{
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int i, j;
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u32 addr = xe_bo_ggtt_addr(ads->bo) + guc_ads_capture_offset(ads);
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/* FIXME: Populate a proper capture list */
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for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
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for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
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ads_blob_write(ads, ads.capture_instance[i][j], addr);
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ads_blob_write(ads, ads.capture_class[i][j], addr);
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}
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ads_blob_write(ads, ads.capture_global[i], addr);
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}
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}
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static void guc_mmio_regset_write_one(struct xe_guc_ads *ads,
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struct iosys_map *regset_map,
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u32 reg, u32 flags,
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unsigned int n_entry)
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{
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struct guc_mmio_reg entry = {
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.offset = reg,
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.flags = flags,
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/* TODO: steering */
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};
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xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),
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&entry, sizeof(entry));
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}
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static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads,
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struct iosys_map *regset_map,
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struct xe_hw_engine *hwe)
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{
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struct xe_hw_engine *hwe_rcs_reset_domain =
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xe_gt_any_hw_engine_by_reset_domain(hwe->gt, XE_ENGINE_CLASS_RENDER);
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struct xe_reg_sr_entry *entry;
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unsigned long idx;
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unsigned count = 0;
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const struct {
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u32 reg;
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u32 flags;
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bool skip;
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} *e, extra_regs[] = {
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{ .reg = RING_MODE_GEN7(hwe->mmio_base).reg, },
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{ .reg = RING_HWS_PGA(hwe->mmio_base).reg, },
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{ .reg = RING_IMR(hwe->mmio_base).reg, },
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{ .reg = GEN12_RCU_MODE.reg, .flags = 0x3,
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.skip = hwe != hwe_rcs_reset_domain },
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};
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u32 i;
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BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX);
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xa_for_each(&hwe->reg_sr.xa, idx, entry) {
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u32 flags = entry->masked_reg ? GUC_REGSET_MASKED : 0;
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guc_mmio_regset_write_one(ads, regset_map, idx, flags, count++);
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}
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for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) {
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if (e->skip)
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continue;
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guc_mmio_regset_write_one(ads, regset_map,
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e->reg, e->flags, count++);
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}
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for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) {
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guc_mmio_regset_write_one(ads, regset_map,
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GEN9_LNCFCMOCS(i).reg, 0, count++);
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}
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XE_BUG_ON(ads->regset_size < (count * sizeof(struct guc_mmio_reg)));
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return count;
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}
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static void guc_mmio_reg_state_init(struct xe_guc_ads *ads)
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{
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size_t regset_offset = guc_ads_regset_offset(ads);
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struct xe_gt *gt = ads_to_gt(ads);
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struct xe_hw_engine *hwe;
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enum xe_hw_engine_id id;
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u32 addr = xe_bo_ggtt_addr(ads->bo) + regset_offset;
|
|
struct iosys_map regset_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
|
|
regset_offset);
|
|
|
|
for_each_hw_engine(hwe, gt, id) {
|
|
unsigned int count;
|
|
u8 gc;
|
|
|
|
/*
|
|
* 1. Write all MMIO entries for this engine to the table. No
|
|
* need to worry about fused-off engines and when there are
|
|
* entries in the regset: the reg_state_list has been zero'ed
|
|
* by xe_guc_ads_populate()
|
|
*/
|
|
count = guc_mmio_regset_write(ads, ®set_map, hwe);
|
|
if (!count)
|
|
continue;
|
|
|
|
/*
|
|
* 2. Record in the header (ads.reg_state_list) the address
|
|
* location and number of entries
|
|
*/
|
|
gc = xe_engine_class_to_guc_class(hwe->class);
|
|
ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr);
|
|
ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count);
|
|
|
|
addr += count * sizeof(struct guc_mmio_reg);
|
|
iosys_map_incr(®set_map, count * sizeof(struct guc_mmio_reg));
|
|
}
|
|
}
|
|
|
|
static void guc_um_init_params(struct xe_guc_ads *ads)
|
|
{
|
|
u32 um_queue_offset = guc_ads_um_queues_offset(ads);
|
|
u64 base_dpa;
|
|
u32 base_ggtt;
|
|
int i;
|
|
|
|
base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset;
|
|
base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset;
|
|
|
|
for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) {
|
|
ads_blob_write(ads, um_init_params.queue_params[i].base_dpa,
|
|
base_dpa + (i * GUC_UM_QUEUE_SIZE));
|
|
ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address,
|
|
base_ggtt + (i * GUC_UM_QUEUE_SIZE));
|
|
ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes,
|
|
GUC_UM_QUEUE_SIZE);
|
|
}
|
|
|
|
ads_blob_write(ads, um_init_params.page_response_timeout_in_us,
|
|
GUC_PAGE_RES_TIMEOUT_US);
|
|
}
|
|
|
|
static void guc_doorbell_init(struct xe_guc_ads *ads)
|
|
{
|
|
struct xe_device *xe = ads_to_xe(ads);
|
|
struct xe_gt *gt = ads_to_gt(ads);
|
|
|
|
if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) {
|
|
u32 distdbreg =
|
|
xe_mmio_read32(gt, GEN12_DIST_DBS_POPULATED.reg);
|
|
|
|
ads_blob_write(ads,
|
|
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
|
|
((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT)
|
|
& GEN12_DOORBELLS_PER_SQIDI) + 1);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* xe_guc_ads_populate_minimal - populate minimal ADS
|
|
* @ads: Additional data structures object
|
|
*
|
|
* This function populates a minimal ADS that does not support submissions but
|
|
* enough so the GuC can load and the hwconfig table can be read.
|
|
*/
|
|
void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads)
|
|
{
|
|
struct xe_gt *gt = ads_to_gt(ads);
|
|
struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
|
|
offsetof(struct __guc_ads_blob, system_info));
|
|
u32 base = xe_bo_ggtt_addr(ads->bo);
|
|
|
|
XE_BUG_ON(!ads->bo);
|
|
|
|
xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size);
|
|
guc_policies_init(ads);
|
|
guc_prep_golden_lrc_null(ads);
|
|
guc_mapping_table_init_invalid(gt, &info_map);
|
|
guc_doorbell_init(ads);
|
|
|
|
ads_blob_write(ads, ads.scheduler_policies, base +
|
|
offsetof(struct __guc_ads_blob, policies));
|
|
ads_blob_write(ads, ads.gt_system_info, base +
|
|
offsetof(struct __guc_ads_blob, system_info));
|
|
ads_blob_write(ads, ads.private_data, base +
|
|
guc_ads_private_data_offset(ads));
|
|
}
|
|
|
|
void xe_guc_ads_populate(struct xe_guc_ads *ads)
|
|
{
|
|
struct xe_device *xe = ads_to_xe(ads);
|
|
struct xe_gt *gt = ads_to_gt(ads);
|
|
struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
|
|
offsetof(struct __guc_ads_blob, system_info));
|
|
u32 base = xe_bo_ggtt_addr(ads->bo);
|
|
|
|
XE_BUG_ON(!ads->bo);
|
|
|
|
xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size);
|
|
guc_policies_init(ads);
|
|
fill_engine_enable_masks(gt, &info_map);
|
|
guc_mmio_reg_state_init(ads);
|
|
guc_prep_golden_lrc_null(ads);
|
|
guc_mapping_table_init(gt, &info_map);
|
|
guc_capture_list_init(ads);
|
|
guc_doorbell_init(ads);
|
|
|
|
if (xe->info.supports_usm) {
|
|
guc_um_init_params(ads);
|
|
ads_blob_write(ads, ads.um_init_data, base +
|
|
offsetof(struct __guc_ads_blob, um_init_params));
|
|
}
|
|
|
|
ads_blob_write(ads, ads.scheduler_policies, base +
|
|
offsetof(struct __guc_ads_blob, policies));
|
|
ads_blob_write(ads, ads.gt_system_info, base +
|
|
offsetof(struct __guc_ads_blob, system_info));
|
|
ads_blob_write(ads, ads.private_data, base +
|
|
guc_ads_private_data_offset(ads));
|
|
}
|
|
|
|
static void guc_populate_golden_lrc(struct xe_guc_ads *ads)
|
|
{
|
|
struct xe_device *xe = ads_to_xe(ads);
|
|
struct xe_gt *gt = ads_to_gt(ads);
|
|
struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
|
|
offsetof(struct __guc_ads_blob, system_info));
|
|
size_t total_size = 0, alloc_size, real_size;
|
|
u32 addr_ggtt, offset;
|
|
int class;
|
|
|
|
offset = guc_ads_golden_lrc_offset(ads);
|
|
addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
|
|
|
|
for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
|
|
u8 guc_class;
|
|
|
|
if (class == XE_ENGINE_CLASS_OTHER)
|
|
continue;
|
|
|
|
guc_class = xe_engine_class_to_guc_class(class);
|
|
|
|
if (!info_map_read(xe, &info_map,
|
|
engine_enabled_masks[guc_class]))
|
|
continue;
|
|
|
|
XE_BUG_ON(!gt->default_lrc[class]);
|
|
|
|
real_size = xe_lrc_size(xe, class);
|
|
alloc_size = PAGE_ALIGN(real_size);
|
|
total_size += alloc_size;
|
|
|
|
/*
|
|
* This interface is slightly confusing. We need to pass the
|
|
* base address of the full golden context and the size of just
|
|
* the engine state, which is the section of the context image
|
|
* that starts after the execlists LRC registers. This is
|
|
* required to allow the GuC to restore just the engine state
|
|
* when a watchdog reset occurs.
|
|
* We calculate the engine state size by removing the size of
|
|
* what comes before it in the context image (which is identical
|
|
* on all engines).
|
|
*/
|
|
ads_blob_write(ads, ads.eng_state_size[guc_class],
|
|
real_size - xe_lrc_skip_size(xe));
|
|
ads_blob_write(ads, ads.golden_context_lrca[guc_class],
|
|
addr_ggtt);
|
|
|
|
xe_map_memcpy_to(xe, ads_to_map(ads), offset,
|
|
gt->default_lrc[class], real_size);
|
|
|
|
addr_ggtt += alloc_size;
|
|
offset += alloc_size;
|
|
}
|
|
|
|
XE_BUG_ON(total_size != ads->golden_lrc_size);
|
|
}
|
|
|
|
void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads)
|
|
{
|
|
guc_populate_golden_lrc(ads);
|
|
}
|