393 lines
10 KiB
C
393 lines
10 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef _XE_GUC_FWIF_H
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#define _XE_GUC_FWIF_H
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#include <linux/bits.h>
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#include "abi/guc_actions_abi.h"
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#include "abi/guc_actions_slpc_abi.h"
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#include "abi/guc_errors_abi.h"
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#include "abi/guc_communication_mmio_abi.h"
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#include "abi/guc_communication_ctb_abi.h"
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#include "abi/guc_klvs_abi.h"
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#include "abi/guc_messages_abi.h"
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#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 4
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#define G2H_LEN_DW_DEREGISTER_CONTEXT 3
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#define G2H_LEN_DW_TLB_INVALIDATE 3
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#define GUC_CONTEXT_DISABLE 0
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#define GUC_CONTEXT_ENABLE 1
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#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
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#define GUC_CLIENT_PRIORITY_HIGH 1
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#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
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#define GUC_CLIENT_PRIORITY_NORMAL 3
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#define GUC_CLIENT_PRIORITY_NUM 4
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#define GUC_RENDER_ENGINE 0
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#define GUC_VIDEO_ENGINE 1
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#define GUC_BLITTER_ENGINE 2
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#define GUC_VIDEOENHANCE_ENGINE 3
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#define GUC_VIDEO_ENGINE2 4
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#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
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#define GUC_RENDER_CLASS 0
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#define GUC_VIDEO_CLASS 1
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#define GUC_VIDEOENHANCE_CLASS 2
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#define GUC_BLITTER_CLASS 3
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#define GUC_COMPUTE_CLASS 4
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#define GUC_GSC_OTHER_CLASS 5
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#define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS
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#define GUC_MAX_ENGINE_CLASSES 16
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#define GUC_MAX_INSTANCES_PER_CLASS 32
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/* Work item for submitting workloads into work queue of GuC. */
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#define WQ_STATUS_ACTIVE 1
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#define WQ_STATUS_SUSPENDED 2
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#define WQ_STATUS_CMD_ERROR 3
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#define WQ_STATUS_ENGINE_ID_NOT_USED 4
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#define WQ_STATUS_SUSPENDED_FROM_RESET 5
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#define WQ_TYPE_NOOP 0x4
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#define WQ_TYPE_MULTI_LRC 0x5
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#define WQ_TYPE_MASK GENMASK(7, 0)
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#define WQ_LEN_MASK GENMASK(26, 16)
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#define WQ_GUC_ID_MASK GENMASK(15, 0)
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#define WQ_RING_TAIL_MASK GENMASK(28, 18)
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struct guc_wq_item {
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u32 header;
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u32 context_desc;
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u32 submit_element_info;
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u32 fence_id;
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} __packed;
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struct guc_sched_wq_desc {
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u32 head;
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u32 tail;
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u32 error_offset;
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u32 wq_status;
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u32 reserved[28];
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} __packed;
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/* Helper for context registration H2G */
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struct guc_ctxt_registration_info {
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u32 flags;
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u32 context_idx;
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u32 engine_class;
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u32 engine_submit_mask;
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u32 wq_desc_lo;
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u32 wq_desc_hi;
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u32 wq_base_lo;
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u32 wq_base_hi;
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u32 wq_size;
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u32 hwlrca_lo;
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u32 hwlrca_hi;
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};
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#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
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/* 32-bit KLV structure as used by policy updates and others */
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struct guc_klv_generic_dw_t {
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u32 kl;
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u32 value;
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} __packed;
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/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
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struct guc_update_engine_policy_header {
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u32 action;
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u32 guc_id;
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} __packed;
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struct guc_update_engine_policy {
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struct guc_update_engine_policy_header header;
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struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
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} __packed;
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/* GUC_CTL_* - Parameters for loading the GuC */
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#define GUC_CTL_LOG_PARAMS 0
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#define GUC_LOG_VALID BIT(0)
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#define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
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#define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
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#define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
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#define GUC_LOG_CRASH_SHIFT 4
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#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
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#define GUC_LOG_DEBUG_SHIFT 6
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#define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
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#define GUC_LOG_CAPTURE_SHIFT 10
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#define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT)
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#define GUC_LOG_BUF_ADDR_SHIFT 12
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#define GUC_CTL_WA 1
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#define GUC_WA_GAM_CREDITS BIT(10)
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#define GUC_WA_DUAL_QUEUE BIT(11)
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#define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
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#define GUC_WA_CONTEXT_ISOLATION BIT(15)
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#define GUC_WA_PRE_PARSER BIT(14)
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#define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
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#define GUC_WA_POLLCS BIT(18)
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#define GUC_WA_RENDER_RST_RC6_EXIT BIT(19)
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#define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
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#define GUC_CTL_FEATURE 2
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#define GUC_CTL_ENABLE_SLPC BIT(2)
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#define GUC_CTL_DISABLE_SCHEDULER BIT(14)
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#define GUC_CTL_DEBUG 3
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#define GUC_LOG_VERBOSITY_SHIFT 0
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#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
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#define GUC_LOG_VERBOSITY_MIN 0
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#define GUC_LOG_VERBOSITY_MAX 3
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#define GUC_LOG_VERBOSITY_MASK 0x0000000f
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#define GUC_LOG_DESTINATION_MASK (3 << 4)
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#define GUC_LOG_DISABLED (1 << 6)
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#define GUC_PROFILE_ENABLED (1 << 7)
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#define GUC_CTL_ADS 4
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#define GUC_ADS_ADDR_SHIFT 1
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#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
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#define GUC_CTL_DEVID 5
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#define GUC_CTL_MAX_DWORDS 14
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/* Scheduling policy settings */
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#define GLOBAL_POLICY_MAX_NUM_WI 15
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/* Don't reset an engine upon preemption failure */
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#define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
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#define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
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struct guc_policies {
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u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
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/* In micro seconds. How much time to allow before DPC processing is
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* called back via interrupt (to prevent DPC queue drain starving).
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* Typically 1000s of micro seconds (example only, not granularity). */
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u32 dpc_promote_time;
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/* Must be set to take these new values. */
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u32 is_valid;
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/* Max number of WIs to process per call. A large value may keep CS
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* idle. */
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u32 max_num_work_items;
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u32 global_flags;
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u32 reserved[4];
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} __packed;
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/* GuC MMIO reg state struct */
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struct guc_mmio_reg {
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u32 offset;
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u32 value;
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u32 flags;
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u32 mask;
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#define GUC_REGSET_MASKED BIT(0)
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#define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
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#define GUC_REGSET_RESTORE_ONLY BIT(3)
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} __packed;
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/* GuC register sets */
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struct guc_mmio_reg_set {
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u32 address;
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u16 count;
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u16 reserved;
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} __packed;
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/* Generic GT SysInfo data types */
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#define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
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#define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
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#define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
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#define GUC_GENERIC_GT_SYSINFO_MAX 16
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/* HW info */
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struct guc_gt_system_info {
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u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
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u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
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} __packed;
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enum {
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GUC_CAPTURE_LIST_INDEX_PF = 0,
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GUC_CAPTURE_LIST_INDEX_VF = 1,
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GUC_CAPTURE_LIST_INDEX_MAX = 2,
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};
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/* GuC Additional Data Struct */
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struct guc_ads {
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struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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u32 reserved0;
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u32 scheduler_policies;
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u32 gt_system_info;
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u32 reserved1;
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u32 control_data;
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u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
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u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
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u32 private_data;
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u32 um_init_data;
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u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
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u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
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u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
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u32 reserved[14];
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} __packed;
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/* Engine usage stats */
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struct guc_engine_usage_record {
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u32 current_context_index;
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u32 last_switch_in_stamp;
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u32 reserved0;
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u32 total_runtime;
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u32 reserved1[4];
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} __packed;
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struct guc_engine_usage {
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struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
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} __packed;
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/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
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enum xe_guc_recv_message {
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XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
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XE_GUC_RECV_MSG_EXCEPTION = BIT(30),
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};
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/* Page fault structures */
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struct access_counter_desc {
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u32 dw0;
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#define ACCESS_COUNTER_TYPE BIT(0)
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#define ACCESS_COUNTER_SUBG_LO GENMASK(31, 1)
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u32 dw1;
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#define ACCESS_COUNTER_SUBG_HI BIT(0)
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#define ACCESS_COUNTER_RSVD0 GENMASK(2, 1)
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#define ACCESS_COUNTER_ENG_INSTANCE GENMASK(8, 3)
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#define ACCESS_COUNTER_ENG_CLASS GENMASK(11, 9)
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#define ACCESS_COUNTER_ASID GENMASK(31, 12)
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u32 dw2;
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#define ACCESS_COUNTER_VFID GENMASK(5, 0)
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#define ACCESS_COUNTER_RSVD1 GENMASK(7, 6)
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#define ACCESS_COUNTER_GRANULARITY GENMASK(10, 8)
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#define ACCESS_COUNTER_RSVD2 GENMASK(16, 11)
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#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)
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u32 dw3;
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#define ACCESS_COUNTER_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)
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} __packed;
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enum guc_um_queue_type {
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GUC_UM_HW_QUEUE_PAGE_FAULT = 0,
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GUC_UM_HW_QUEUE_PAGE_FAULT_RESPONSE,
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GUC_UM_HW_QUEUE_ACCESS_COUNTER,
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GUC_UM_HW_QUEUE_MAX
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};
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struct guc_um_queue_params {
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u64 base_dpa;
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u32 base_ggtt_address;
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u32 size_in_bytes;
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u32 rsvd[4];
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} __packed;
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struct guc_um_init_params {
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u64 page_response_timeout_in_us;
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u32 rsvd[6];
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struct guc_um_queue_params queue_params[GUC_UM_HW_QUEUE_MAX];
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} __packed;
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enum xe_guc_fault_reply_type {
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PFR_ACCESS = 0,
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PFR_ENGINE,
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PFR_VFID,
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PFR_ALL,
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PFR_INVALID
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};
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enum xe_guc_response_desc_type {
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TLB_INVALIDATION_DESC = 0,
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FAULT_RESPONSE_DESC
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};
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struct xe_guc_pagefault_desc {
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u32 dw0;
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#define PFD_FAULT_LEVEL GENMASK(2, 0)
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#define PFD_SRC_ID GENMASK(10, 3)
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#define PFD_RSVD_0 GENMASK(17, 11)
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#define XE2_PFD_TRVA_FAULT BIT(18)
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#define PFD_ENG_INSTANCE GENMASK(24, 19)
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#define PFD_ENG_CLASS GENMASK(27, 25)
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#define PFD_PDATA_LO GENMASK(31, 28)
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u32 dw1;
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#define PFD_PDATA_HI GENMASK(11, 0)
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#define PFD_PDATA_HI_SHIFT 4
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#define PFD_ASID GENMASK(31, 12)
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u32 dw2;
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#define PFD_ACCESS_TYPE GENMASK(1, 0)
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#define PFD_FAULT_TYPE GENMASK(3, 2)
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#define PFD_VFID GENMASK(9, 4)
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#define PFD_RSVD_1 GENMASK(11, 10)
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#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12)
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#define PFD_VIRTUAL_ADDR_LO_SHIFT 12
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u32 dw3;
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#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0)
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#define PFD_VIRTUAL_ADDR_HI_SHIFT 32
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} __packed;
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struct xe_guc_pagefault_reply {
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u32 dw0;
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#define PFR_VALID BIT(0)
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#define PFR_SUCCESS BIT(1)
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#define PFR_REPLY GENMASK(4, 2)
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#define PFR_RSVD_0 GENMASK(9, 5)
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#define PFR_DESC_TYPE GENMASK(11, 10)
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#define PFR_ASID GENMASK(31, 12)
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u32 dw1;
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#define PFR_VFID GENMASK(5, 0)
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#define PFR_RSVD_1 BIT(6)
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#define PFR_ENG_INSTANCE GENMASK(12, 7)
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#define PFR_ENG_CLASS GENMASK(15, 13)
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#define PFR_PDATA GENMASK(31, 16)
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u32 dw2;
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#define PFR_RSVD_2 GENMASK(31, 0)
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} __packed;
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struct xe_guc_acc_desc {
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u32 dw0;
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#define ACC_TYPE BIT(0)
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#define ACC_TRIGGER 0
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#define ACC_NOTIFY 1
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#define ACC_SUBG_LO GENMASK(31, 1)
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u32 dw1;
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#define ACC_SUBG_HI BIT(0)
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#define ACC_RSVD0 GENMASK(2, 1)
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#define ACC_ENG_INSTANCE GENMASK(8, 3)
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#define ACC_ENG_CLASS GENMASK(11, 9)
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#define ACC_ASID GENMASK(31, 12)
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u32 dw2;
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#define ACC_VFID GENMASK(5, 0)
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#define ACC_RSVD1 GENMASK(7, 6)
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#define ACC_GRANULARITY GENMASK(10, 8)
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#define ACC_RSVD2 GENMASK(16, 11)
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#define ACC_VIRTUAL_ADDR_RANGE_LO GENMASK(31, 17)
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u32 dw3;
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#define ACC_VIRTUAL_ADDR_RANGE_HI GENMASK(31, 0)
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} __packed;
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#endif
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