Markos Chandras cf0a8aa022 MIPS: cpu-probe: Set the FTLB probability bit on supported cores ... Make use of the Config6/FLTBP bit to set the probability of a TLBWR instruction to hit the FTLB or the VTLB. A value of 0 (which may be the default value on certain cores, such as proAptiv or P5600) means that a TLBWR instruction will never hit the VTLB which leads to performance limitations since it effectively decreases the number of available TLB slots. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8368/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2014-11-24 07:44:05 +01:00
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asm	MIPS: cpu-probe: Set the FTLB probability bit on supported cores	2014-11-24 07:44:05 +01:00
uapi/asm	MIPS: Fix a copy & paste error in unistd.h	2014-11-24 07:44:03 +01:00