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02c981c07b
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/*
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* reset controller for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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void __iomem *sirfsoc_rstc_base;
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static DEFINE_MUTEX(rstc_lock);
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static struct of_device_id rstc_ids[] = {
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{ .compatible = "sirf,prima2-rstc" },
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};
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static int __init sirfsoc_of_rstc_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, rstc_ids);
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if (!np)
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panic("unable to find compatible rstc node in dtb\n");
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sirfsoc_rstc_base = of_iomap(np, 0);
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if (!sirfsoc_rstc_base)
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panic("unable to map rstc cpu registers\n");
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of_node_put(np);
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return 0;
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}
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early_initcall(sirfsoc_of_rstc_init);
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int sirfsoc_reset_device(struct device *dev)
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{
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const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
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unsigned int reset_bit;
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if (!prop)
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return -ENODEV;
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reset_bit = be32_to_cpup(prop);
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mutex_lock(&rstc_lock);
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/*
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* Writing 1 to this bit resets corresponding block. Writing 0 to this
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* bit de-asserts reset signal of the corresponding block.
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* datasheet doesn't require explicit delay between the set and clear
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* of reset bit. it could be shorter if tests pass.
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*/
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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msleep(10);
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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mutex_unlock(&rstc_lock);
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return 0;
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}
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