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6e29032340
The topology IDs which identify the LLC and L2 domains clearly belong to the per CPU topology information. Move them into cpuinfo_x86::cpuinfo_topo and get rid of the extra per CPU data and the related exports. This also paves the way to do proper topology evaluation during early boot because it removes the only per CPU dependency for that. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Sohil Mehta <sohil.mehta@intel.com> Tested-by: Michael Kelley <mikelley@microsoft.com> Tested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Tested-by: Zhang Rui <rui.zhang@intel.com> Reviewed-by: Arjan van de Ven <arjan@linux.intel.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20230814085112.803864641@linutronix.de
18 lines
485 B
C
18 lines
485 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CACHEINFO_H
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#define _ASM_X86_CACHEINFO_H
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/* Kernel controls MTRR and/or PAT MSRs. */
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extern unsigned int memory_caching_control;
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#define CACHE_MTRR 0x01
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#define CACHE_PAT 0x02
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void cache_disable(void);
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void cache_enable(void);
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void set_cache_aps_delayed_init(bool val);
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bool get_cache_aps_delayed_init(void);
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void cache_bp_init(void);
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void cache_bp_restore(void);
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void cache_aps_init(void);
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#endif /* _ASM_X86_CACHEINFO_H */
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