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a5f6c2ace9
A control-protection fault is triggered when a control-flow transfer attempt violates Shadow Stack or Indirect Branch Tracking constraints. For example, the return address for a RET instruction differs from the copy on the shadow stack. There already exists a control-protection fault handler for handling kernel IBT faults. Refactor this fault handler into separate user and kernel handlers, like the page fault handler. Add a control-protection handler for usermode. To avoid ifdeffery, put them both in a new file cet.c, which is compiled in the case of either of the two CET features supported in the kernel: kernel IBT or user mode shadow stack. Move some static inline functions from traps.c into a header so they can be used in cet.c. Opportunistically fix a comment in the kernel IBT part of the fault handler that is on the end of the line instead of preceding it. Keep the same behavior for the kernel side of the fault handler, except for converting a BUG to a WARN in the case of a #CP happening when the feature is missing. This unifies the behavior with the new shadow stack code, and also prevents the kernel from crashing under this situation which is potentially recoverable. The control-protection fault handler works in a similar way as the general protection fault handler. It provides the si_code SEGV_CPERR to the signal handler. Co-developed-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Kees Cook <keescook@chromium.org> Acked-by: Mike Rapoport (IBM) <rppt@kernel.org> Tested-by: Pengfei Xu <pengfei.xu@intel.com> Tested-by: John Allen <john.allen@amd.com> Tested-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/all/20230613001108.3040476-28-rick.p.edgecombe%40intel.com
148 lines
3.8 KiB
C
148 lines
3.8 KiB
C
#ifndef _ASM_X86_DISABLED_FEATURES_H
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#define _ASM_X86_DISABLED_FEATURES_H
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/* These features, although they might be available in a CPU
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* will not be used because the compile options to support
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* them are not present.
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*
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* This code allows them to be checked and disabled at
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* compile time without an explicit #ifdef. Use
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* cpu_feature_enabled().
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*/
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#ifdef CONFIG_X86_UMIP
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# define DISABLE_UMIP 0
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#else
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# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31))
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#endif
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#ifdef CONFIG_X86_64
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# define DISABLE_VME (1<<(X86_FEATURE_VME & 31))
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# define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31))
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# define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31))
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# define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31))
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# define DISABLE_PCID 0
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#else
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# define DISABLE_VME 0
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# define DISABLE_K6_MTRR 0
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# define DISABLE_CYRIX_ARR 0
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# define DISABLE_CENTAUR_MCR 0
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# define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31))
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#endif /* CONFIG_X86_64 */
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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# define DISABLE_PKU 0
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# define DISABLE_OSPKE 0
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#else
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# define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31))
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# define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31))
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#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
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#ifdef CONFIG_X86_5LEVEL
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# define DISABLE_LA57 0
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#else
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# define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31))
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#endif
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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# define DISABLE_PTI 0
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#else
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# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
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#endif
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#ifdef CONFIG_RETPOLINE
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# define DISABLE_RETPOLINE 0
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#else
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# define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \
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(1 << (X86_FEATURE_RETPOLINE_LFENCE & 31)))
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#endif
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#ifdef CONFIG_RETHUNK
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# define DISABLE_RETHUNK 0
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#else
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# define DISABLE_RETHUNK (1 << (X86_FEATURE_RETHUNK & 31))
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#endif
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#ifdef CONFIG_CPU_UNRET_ENTRY
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# define DISABLE_UNRET 0
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#else
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# define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31))
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#endif
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#ifdef CONFIG_CALL_DEPTH_TRACKING
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# define DISABLE_CALL_DEPTH_TRACKING 0
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#else
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# define DISABLE_CALL_DEPTH_TRACKING (1 << (X86_FEATURE_CALL_DEPTH & 31))
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#endif
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#ifdef CONFIG_ADDRESS_MASKING
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# define DISABLE_LAM 0
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#else
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# define DISABLE_LAM (1 << (X86_FEATURE_LAM & 31))
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#endif
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#ifdef CONFIG_INTEL_IOMMU_SVM
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# define DISABLE_ENQCMD 0
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#else
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# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31))
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#endif
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#ifdef CONFIG_X86_SGX
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# define DISABLE_SGX 0
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#else
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# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31))
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#endif
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#ifdef CONFIG_XEN_PV
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# define DISABLE_XENPV 0
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#else
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# define DISABLE_XENPV (1 << (X86_FEATURE_XENPV & 31))
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#endif
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#ifdef CONFIG_INTEL_TDX_GUEST
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# define DISABLE_TDX_GUEST 0
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#else
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# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31))
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#endif
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#ifdef CONFIG_X86_USER_SHADOW_STACK
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#define DISABLE_USER_SHSTK 0
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#else
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#define DISABLE_USER_SHSTK (1 << (X86_FEATURE_USER_SHSTK & 31))
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#endif
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#ifdef CONFIG_X86_KERNEL_IBT
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#define DISABLE_IBT 0
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#else
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#define DISABLE_IBT (1 << (X86_FEATURE_IBT & 31))
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#endif
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/*
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* Make sure to add features to the correct mask
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*/
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#define DISABLED_MASK0 (DISABLE_VME)
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#define DISABLED_MASK1 0
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#define DISABLED_MASK2 0
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#define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR)
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#define DISABLED_MASK4 (DISABLE_PCID)
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#define DISABLED_MASK5 0
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#define DISABLED_MASK6 0
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#define DISABLED_MASK7 (DISABLE_PTI)
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#define DISABLED_MASK8 (DISABLE_XENPV|DISABLE_TDX_GUEST)
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#define DISABLED_MASK9 (DISABLE_SGX)
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#define DISABLED_MASK10 0
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#define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET| \
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DISABLE_CALL_DEPTH_TRACKING|DISABLE_USER_SHSTK)
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#define DISABLED_MASK12 (DISABLE_LAM)
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#define DISABLED_MASK13 0
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#define DISABLED_MASK14 0
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#define DISABLED_MASK15 0
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#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \
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DISABLE_ENQCMD)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 (DISABLE_IBT)
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#define DISABLED_MASK19 0
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#define DISABLED_MASK20 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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