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6a25bd4d1d
The Atmel SAM9x5 SMD clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on. Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Claudiu Beznea <claudiu.beznea@microchip.com> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-49-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
142 lines
3.3 KiB
C
142 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define SMD_DIV_SHIFT 8
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#define SMD_MAX_DIV 0xf
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struct at91sam9x5_clk_smd {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_at91sam9x5_clk_smd(hw) \
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container_of(hw, struct at91sam9x5_clk_smd, hw)
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static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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unsigned int smdr;
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u8 smddiv;
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regmap_read(smd->regmap, AT91_PMC_SMD, &smdr);
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smddiv = (smdr & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
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return parent_rate / (smddiv + 1);
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}
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static int at91sam9x5_clk_smd_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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unsigned long div;
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unsigned long bestrate;
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unsigned long tmp;
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if (req->rate >= req->best_parent_rate) {
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req->rate = req->best_parent_rate;
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return 0;
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}
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div = req->best_parent_rate / req->rate;
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if (div > SMD_MAX_DIV) {
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req->rate = req->best_parent_rate / (SMD_MAX_DIV + 1);
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return 0;
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}
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bestrate = req->best_parent_rate / div;
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tmp = req->best_parent_rate / (div + 1);
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if (bestrate - req->rate > req->rate - tmp)
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bestrate = tmp;
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req->rate = bestrate;
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return 0;
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}
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static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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if (index > 1)
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return -EINVAL;
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regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMDS,
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index ? AT91_PMC_SMDS : 0);
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return 0;
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}
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static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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unsigned int smdr;
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regmap_read(smd->regmap, AT91_PMC_SMD, &smdr);
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return smdr & AT91_PMC_SMDS;
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}
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static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
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unsigned long div = parent_rate / rate;
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if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
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return -EINVAL;
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regmap_update_bits(smd->regmap, AT91_PMC_SMD, AT91_PMC_SMD_DIV,
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(div - 1) << SMD_DIV_SHIFT);
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return 0;
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}
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static const struct clk_ops at91sam9x5_smd_ops = {
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.recalc_rate = at91sam9x5_clk_smd_recalc_rate,
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.determine_rate = at91sam9x5_clk_smd_determine_rate,
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.get_parent = at91sam9x5_clk_smd_get_parent,
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.set_parent = at91sam9x5_clk_smd_set_parent,
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.set_rate = at91sam9x5_clk_smd_set_rate,
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};
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struct clk_hw * __init
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at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
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const char **parent_names, u8 num_parents)
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{
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struct at91sam9x5_clk_smd *smd;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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smd = kzalloc(sizeof(*smd), GFP_KERNEL);
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if (!smd)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &at91sam9x5_smd_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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smd->hw.init = &init;
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smd->regmap = regmap;
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hw = &smd->hw;
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ret = clk_hw_register(NULL, &smd->hw);
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if (ret) {
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kfree(smd);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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