Nishanth Menon de60edf1be arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs ... Though GIC ARE option is disabled for no GIC-v2 compatibility, Cortex-A53 is free to implement the CPU interface as long as it communicates with the GIC using the stream protocol. This requires that the SoC integration mark out the PERIPHBASE[1] as reserved area within the SoC. See longer discussion in [2] for further information. Update the GIC register map to indicate offsets from PERIPHBASE based on [3]. Without doing this, systems like kvm will not function with gic-v2 emulation. [1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1 [2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/ [3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map Cc: stable@vger.kernel.org Fixes: 8abae9389b ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220215201008.15235-5-nm@ti.com		2022-02-22 11:04:12 -06:00
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dts	arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs	2022-02-22 11:04:12 -06:00
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install.sh
Makefile	arm64: move the (z)install rules to arch/arm64/Makefile	2021-08-03 16:19:03 +01:00