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95711cd5f0
This driver (currently) only takes control of the switch chip over SPI and configures it to route packages around when connected to a CPU port. But Vitesse chip support also parallel interface. This patch split driver into two parts: core and spi. It is required for add support to another managing interface. Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
203 lines
4.6 KiB
C
203 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* DSA driver for:
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* Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
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* Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
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* Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
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* Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
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*
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* This driver takes control of the switch chip over SPI and
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* configures it to route packages around when connected to a CPU port.
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*
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* Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
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* Includes portions of code from the firmware uploader by:
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/spi/spi.h>
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#include "vitesse-vsc73xx.h"
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#define VSC73XX_CMD_SPI_MODE_READ 0
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#define VSC73XX_CMD_SPI_MODE_WRITE 1
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#define VSC73XX_CMD_SPI_MODE_SHIFT 4
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#define VSC73XX_CMD_SPI_BLOCK_SHIFT 5
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#define VSC73XX_CMD_SPI_BLOCK_MASK 0x7
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#define VSC73XX_CMD_SPI_SUBBLOCK_MASK 0xf
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/**
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* struct vsc73xx_spi - VSC73xx SPI state container
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*/
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struct vsc73xx_spi {
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struct spi_device *spi;
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struct mutex lock; /* Protects SPI traffic */
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struct vsc73xx vsc;
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};
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static const struct vsc73xx_ops vsc73xx_spi_ops;
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static u8 vsc73xx_make_addr(u8 mode, u8 block, u8 subblock)
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{
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u8 ret;
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ret =
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(block & VSC73XX_CMD_SPI_BLOCK_MASK) << VSC73XX_CMD_SPI_BLOCK_SHIFT;
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ret |= (mode & 1) << VSC73XX_CMD_SPI_MODE_SHIFT;
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ret |= subblock & VSC73XX_CMD_SPI_SUBBLOCK_MASK;
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return ret;
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}
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static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
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u32 *val)
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{
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struct vsc73xx_spi *vsc_spi = vsc->priv;
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struct spi_transfer t[2];
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struct spi_message m;
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u8 cmd[4];
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u8 buf[4];
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int ret;
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if (!vsc73xx_is_addr_valid(block, subblock))
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return -EINVAL;
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spi_message_init(&m);
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memset(&t, 0, sizeof(t));
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t[0].tx_buf = cmd;
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t[0].len = sizeof(cmd);
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = sizeof(buf);
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spi_message_add_tail(&t[1], &m);
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cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_READ, block, subblock);
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cmd[1] = reg;
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cmd[2] = 0;
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cmd[3] = 0;
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mutex_lock(&vsc_spi->lock);
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ret = spi_sync(vsc_spi->spi, &m);
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mutex_unlock(&vsc_spi->lock);
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if (ret)
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return ret;
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*val = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
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return 0;
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}
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static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
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u32 val)
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{
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struct vsc73xx_spi *vsc_spi = vsc->priv;
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struct spi_transfer t[2];
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struct spi_message m;
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u8 cmd[2];
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u8 buf[4];
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int ret;
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if (!vsc73xx_is_addr_valid(block, subblock))
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return -EINVAL;
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spi_message_init(&m);
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memset(&t, 0, sizeof(t));
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t[0].tx_buf = cmd;
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t[0].len = sizeof(cmd);
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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t[1].len = sizeof(buf);
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spi_message_add_tail(&t[1], &m);
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cmd[0] = vsc73xx_make_addr(VSC73XX_CMD_SPI_MODE_WRITE, block, subblock);
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cmd[1] = reg;
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buf[0] = (val >> 24) & 0xff;
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buf[1] = (val >> 16) & 0xff;
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buf[2] = (val >> 8) & 0xff;
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buf[3] = val & 0xff;
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mutex_lock(&vsc_spi->lock);
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ret = spi_sync(vsc_spi->spi, &m);
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mutex_unlock(&vsc_spi->lock);
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return ret;
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}
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static int vsc73xx_spi_probe(struct spi_device *spi)
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{
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struct device *dev = &spi->dev;
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struct vsc73xx_spi *vsc_spi;
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int ret;
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vsc_spi = devm_kzalloc(dev, sizeof(*vsc_spi), GFP_KERNEL);
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if (!vsc_spi)
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return -ENOMEM;
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spi_set_drvdata(spi, vsc_spi);
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vsc_spi->spi = spi_dev_get(spi);
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vsc_spi->vsc.dev = dev;
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vsc_spi->vsc.priv = vsc_spi;
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vsc_spi->vsc.ops = &vsc73xx_spi_ops;
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mutex_init(&vsc_spi->lock);
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spi->mode = SPI_MODE_0;
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spi->bits_per_word = 8;
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ret = spi_setup(spi);
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if (ret < 0) {
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dev_err(dev, "spi setup failed.\n");
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return ret;
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}
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return vsc73xx_probe(&vsc_spi->vsc);
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}
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static int vsc73xx_spi_remove(struct spi_device *spi)
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{
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struct vsc73xx_spi *vsc_spi = spi_get_drvdata(spi);
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return vsc73xx_remove(&vsc_spi->vsc);
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}
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static const struct vsc73xx_ops vsc73xx_spi_ops = {
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.read = vsc73xx_spi_read,
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.write = vsc73xx_spi_write,
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};
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static const struct of_device_id vsc73xx_of_match[] = {
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{
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.compatible = "vitesse,vsc7385",
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},
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{
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.compatible = "vitesse,vsc7388",
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},
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{
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.compatible = "vitesse,vsc7395",
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},
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{
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.compatible = "vitesse,vsc7398",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, vsc73xx_of_match);
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static struct spi_driver vsc73xx_spi_driver = {
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.probe = vsc73xx_spi_probe,
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.remove = vsc73xx_spi_remove,
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.driver = {
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.name = "vsc73xx-spi",
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.of_match_table = vsc73xx_of_match,
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},
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};
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module_spi_driver(vsc73xx_spi_driver);
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MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
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MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 SPI driver");
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MODULE_LICENSE("GPL v2");
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