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![Thomas Gleixner](/assets/img/avatar_default.png)
Add SPDX license identifiers to all files which: - Have no license information of any form - Have MODULE_LICENCE("GPL*") inside which was used in the initial scan/conversion to ignore the file These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
542 lines
13 KiB
C
542 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD am53c974 driver.
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* Copyright (c) 2014 Hannes Reinecke, SUSE Linux GmbH
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <scsi/scsi_host.h>
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#include "esp_scsi.h"
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#define DRV_MODULE_NAME "am53c974"
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#define DRV_MODULE_VERSION "1.00"
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static bool am53c974_debug;
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static bool am53c974_fenab = true;
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#define esp_dma_log(f, a...) \
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do { \
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if (am53c974_debug) \
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shost_printk(KERN_DEBUG, esp->host, f, ##a); \
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} while (0)
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#define ESP_DMA_CMD 0x10
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#define ESP_DMA_STC 0x11
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#define ESP_DMA_SPA 0x12
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#define ESP_DMA_WBC 0x13
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#define ESP_DMA_WAC 0x14
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#define ESP_DMA_STATUS 0x15
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#define ESP_DMA_SMDLA 0x16
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#define ESP_DMA_WMAC 0x17
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#define ESP_DMA_CMD_IDLE 0x00
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#define ESP_DMA_CMD_BLAST 0x01
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#define ESP_DMA_CMD_ABORT 0x02
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#define ESP_DMA_CMD_START 0x03
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#define ESP_DMA_CMD_MASK 0x03
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#define ESP_DMA_CMD_DIAG 0x04
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#define ESP_DMA_CMD_MDL 0x10
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#define ESP_DMA_CMD_INTE_P 0x20
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#define ESP_DMA_CMD_INTE_D 0x40
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#define ESP_DMA_CMD_DIR 0x80
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#define ESP_DMA_STAT_PWDN 0x01
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#define ESP_DMA_STAT_ERROR 0x02
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#define ESP_DMA_STAT_ABORT 0x04
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#define ESP_DMA_STAT_DONE 0x08
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#define ESP_DMA_STAT_SCSIINT 0x10
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#define ESP_DMA_STAT_BCMPLT 0x20
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/* EEPROM is accessed with 16-bit values */
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#define DC390_EEPROM_READ 0x80
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#define DC390_EEPROM_LEN 0x40
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/*
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* DC390 EEPROM
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*
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* 8 * 4 bytes of per-device options
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* followed by HBA specific options
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*/
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/* Per-device options */
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#define DC390_EE_MODE1 0x00
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#define DC390_EE_SPEED 0x01
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/* HBA-specific options */
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#define DC390_EE_ADAPT_SCSI_ID 0x40
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#define DC390_EE_MODE2 0x41
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#define DC390_EE_DELAY 0x42
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#define DC390_EE_TAG_CMD_NUM 0x43
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#define DC390_EE_MODE1_PARITY_CHK 0x01
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#define DC390_EE_MODE1_SYNC_NEGO 0x02
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#define DC390_EE_MODE1_EN_DISC 0x04
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#define DC390_EE_MODE1_SEND_START 0x08
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#define DC390_EE_MODE1_TCQ 0x10
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#define DC390_EE_MODE2_MORE_2DRV 0x01
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#define DC390_EE_MODE2_GREATER_1G 0x02
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#define DC390_EE_MODE2_RST_SCSI_BUS 0x04
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#define DC390_EE_MODE2_ACTIVE_NEGATION 0x08
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#define DC390_EE_MODE2_NO_SEEK 0x10
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#define DC390_EE_MODE2_LUN_CHECK 0x20
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struct pci_esp_priv {
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struct esp *esp;
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u8 dma_status;
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};
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static void pci_esp_dma_drain(struct esp *esp);
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static inline struct pci_esp_priv *pci_esp_get_priv(struct esp *esp)
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{
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return dev_get_drvdata(esp->dev);
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}
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static void pci_esp_write8(struct esp *esp, u8 val, unsigned long reg)
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{
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iowrite8(val, esp->regs + (reg * 4UL));
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}
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static u8 pci_esp_read8(struct esp *esp, unsigned long reg)
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{
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return ioread8(esp->regs + (reg * 4UL));
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}
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static void pci_esp_write32(struct esp *esp, u32 val, unsigned long reg)
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{
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return iowrite32(val, esp->regs + (reg * 4UL));
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}
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static int pci_esp_irq_pending(struct esp *esp)
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{
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struct pci_esp_priv *pep = pci_esp_get_priv(esp);
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pep->dma_status = pci_esp_read8(esp, ESP_DMA_STATUS);
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esp_dma_log("dma intr dreg[%02x]\n", pep->dma_status);
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if (pep->dma_status & (ESP_DMA_STAT_ERROR |
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ESP_DMA_STAT_ABORT |
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ESP_DMA_STAT_DONE |
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ESP_DMA_STAT_SCSIINT))
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return 1;
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return 0;
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}
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static void pci_esp_reset_dma(struct esp *esp)
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{
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/* Nothing to do ? */
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}
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static void pci_esp_dma_drain(struct esp *esp)
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{
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u8 resid;
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int lim = 1000;
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if ((esp->sreg & ESP_STAT_PMASK) == ESP_DOP ||
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(esp->sreg & ESP_STAT_PMASK) == ESP_DIP)
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/* Data-In or Data-Out, nothing to be done */
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return;
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while (--lim > 0) {
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resid = pci_esp_read8(esp, ESP_FFLAGS) & ESP_FF_FBYTES;
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if (resid <= 1)
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break;
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cpu_relax();
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}
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/*
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* When there is a residual BCMPLT will never be set
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* (obviously). But we still have to issue the BLAST
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* command, otherwise the data will not being transferred.
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* But we'll never know when the BLAST operation is
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* finished. So check for some time and give up eventually.
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*/
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lim = 1000;
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pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_BLAST, ESP_DMA_CMD);
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while (pci_esp_read8(esp, ESP_DMA_STATUS) & ESP_DMA_STAT_BCMPLT) {
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if (--lim == 0)
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break;
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cpu_relax();
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}
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pci_esp_write8(esp, ESP_DMA_CMD_DIR | ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
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esp_dma_log("DMA blast done (%d tries, %d bytes left)\n", lim, resid);
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/* BLAST residual handling is currently untested */
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if (WARN_ON_ONCE(resid == 1)) {
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struct esp_cmd_entry *ent = esp->active_cmd;
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ent->flags |= ESP_CMD_FLAG_RESIDUAL;
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}
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}
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static void pci_esp_dma_invalidate(struct esp *esp)
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{
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struct pci_esp_priv *pep = pci_esp_get_priv(esp);
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esp_dma_log("invalidate DMA\n");
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pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
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pep->dma_status = 0;
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}
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static int pci_esp_dma_error(struct esp *esp)
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{
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struct pci_esp_priv *pep = pci_esp_get_priv(esp);
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if (pep->dma_status & ESP_DMA_STAT_ERROR) {
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u8 dma_cmd = pci_esp_read8(esp, ESP_DMA_CMD);
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if ((dma_cmd & ESP_DMA_CMD_MASK) == ESP_DMA_CMD_START)
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pci_esp_write8(esp, ESP_DMA_CMD_ABORT, ESP_DMA_CMD);
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return 1;
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}
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if (pep->dma_status & ESP_DMA_STAT_ABORT) {
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pci_esp_write8(esp, ESP_DMA_CMD_IDLE, ESP_DMA_CMD);
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pep->dma_status = pci_esp_read8(esp, ESP_DMA_CMD);
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return 1;
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}
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return 0;
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}
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static void pci_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
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u32 dma_count, int write, u8 cmd)
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{
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struct pci_esp_priv *pep = pci_esp_get_priv(esp);
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u32 val = 0;
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BUG_ON(!(cmd & ESP_CMD_DMA));
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pep->dma_status = 0;
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/* Set DMA engine to IDLE */
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if (write)
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/* DMA write direction logic is inverted */
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val |= ESP_DMA_CMD_DIR;
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pci_esp_write8(esp, ESP_DMA_CMD_IDLE | val, ESP_DMA_CMD);
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pci_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
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pci_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
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if (esp->config2 & ESP_CONFIG2_FENAB)
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pci_esp_write8(esp, (esp_count >> 16) & 0xff, ESP_TCHI);
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pci_esp_write32(esp, esp_count, ESP_DMA_STC);
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pci_esp_write32(esp, addr, ESP_DMA_SPA);
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esp_dma_log("start dma addr[%x] count[%d:%d]\n",
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addr, esp_count, dma_count);
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scsi_esp_cmd(esp, cmd);
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/* Send DMA Start command */
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pci_esp_write8(esp, ESP_DMA_CMD_START | val, ESP_DMA_CMD);
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}
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static u32 pci_esp_dma_length_limit(struct esp *esp, u32 dma_addr, u32 dma_len)
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{
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int dma_limit = 16;
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u32 base, end;
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/*
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* If CONFIG2_FENAB is set we can
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* handle up to 24 bit addresses
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*/
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if (esp->config2 & ESP_CONFIG2_FENAB)
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dma_limit = 24;
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if (dma_len > (1U << dma_limit))
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dma_len = (1U << dma_limit);
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/*
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* Prevent crossing a 24-bit address boundary.
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*/
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base = dma_addr & ((1U << 24) - 1U);
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end = base + dma_len;
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if (end > (1U << 24))
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end = (1U <<24);
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dma_len = end - base;
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return dma_len;
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}
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static const struct esp_driver_ops pci_esp_ops = {
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.esp_write8 = pci_esp_write8,
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.esp_read8 = pci_esp_read8,
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.irq_pending = pci_esp_irq_pending,
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.reset_dma = pci_esp_reset_dma,
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.dma_drain = pci_esp_dma_drain,
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.dma_invalidate = pci_esp_dma_invalidate,
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.send_dma_cmd = pci_esp_send_dma_cmd,
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.dma_error = pci_esp_dma_error,
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.dma_length_limit = pci_esp_dma_length_limit,
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};
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/*
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* Read DC-390 eeprom
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*/
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static void dc390_eeprom_prepare_read(struct pci_dev *pdev, u8 cmd)
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{
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u8 carry_flag = 1, j = 0x80, bval;
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int i;
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for (i = 0; i < 9; i++) {
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if (carry_flag) {
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pci_write_config_byte(pdev, 0x80, 0x40);
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bval = 0xc0;
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} else
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bval = 0x80;
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udelay(160);
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pci_write_config_byte(pdev, 0x80, bval);
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udelay(160);
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pci_write_config_byte(pdev, 0x80, 0);
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udelay(160);
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carry_flag = (cmd & j) ? 1 : 0;
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j >>= 1;
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}
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}
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static u16 dc390_eeprom_get_data(struct pci_dev *pdev)
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{
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int i;
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u16 wval = 0;
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u8 bval;
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for (i = 0; i < 16; i++) {
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wval <<= 1;
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pci_write_config_byte(pdev, 0x80, 0x80);
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udelay(160);
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pci_write_config_byte(pdev, 0x80, 0x40);
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udelay(160);
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pci_read_config_byte(pdev, 0x00, &bval);
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if (bval == 0x22)
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wval |= 1;
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}
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return wval;
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}
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static void dc390_read_eeprom(struct pci_dev *pdev, u16 *ptr)
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{
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u8 cmd = DC390_EEPROM_READ, i;
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for (i = 0; i < DC390_EEPROM_LEN; i++) {
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pci_write_config_byte(pdev, 0xc0, 0);
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udelay(160);
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dc390_eeprom_prepare_read(pdev, cmd++);
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*ptr++ = dc390_eeprom_get_data(pdev);
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pci_write_config_byte(pdev, 0x80, 0);
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pci_write_config_byte(pdev, 0x80, 0);
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udelay(160);
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}
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}
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static void dc390_check_eeprom(struct esp *esp)
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{
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struct pci_dev *pdev = to_pci_dev(esp->dev);
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u8 EEbuf[128];
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u16 *ptr = (u16 *)EEbuf, wval = 0;
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int i;
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dc390_read_eeprom(pdev, ptr);
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for (i = 0; i < DC390_EEPROM_LEN; i++, ptr++)
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wval += *ptr;
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/* no Tekram EEprom found */
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if (wval != 0x1234) {
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dev_printk(KERN_INFO, &pdev->dev,
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"No valid Tekram EEprom found\n");
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return;
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}
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esp->scsi_id = EEbuf[DC390_EE_ADAPT_SCSI_ID];
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esp->num_tags = 2 << EEbuf[DC390_EE_TAG_CMD_NUM];
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if (EEbuf[DC390_EE_MODE2] & DC390_EE_MODE2_ACTIVE_NEGATION)
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esp->config4 |= ESP_CONFIG4_RADE | ESP_CONFIG4_RAE;
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}
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static int pci_esp_probe_one(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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struct scsi_host_template *hostt = &scsi_esp_template;
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int err = -ENODEV;
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struct Scsi_Host *shost;
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struct esp *esp;
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struct pci_esp_priv *pep;
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if (pci_enable_device(pdev)) {
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dev_printk(KERN_INFO, &pdev->dev, "cannot enable device\n");
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return -ENODEV;
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}
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if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
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dev_printk(KERN_INFO, &pdev->dev,
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"failed to set 32bit DMA mask\n");
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goto fail_disable_device;
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}
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shost = scsi_host_alloc(hostt, sizeof(struct esp));
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if (!shost) {
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dev_printk(KERN_INFO, &pdev->dev,
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"failed to allocate scsi host\n");
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err = -ENOMEM;
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goto fail_disable_device;
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}
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pep = kzalloc(sizeof(struct pci_esp_priv), GFP_KERNEL);
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if (!pep) {
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dev_printk(KERN_INFO, &pdev->dev,
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"failed to allocate esp_priv\n");
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err = -ENOMEM;
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goto fail_host_alloc;
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}
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esp = shost_priv(shost);
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esp->host = shost;
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esp->dev = &pdev->dev;
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esp->ops = &pci_esp_ops;
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/*
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* The am53c974 HBA has a design flaw of generating
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* spurious DMA completion interrupts when using
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* DMA for command submission.
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*/
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esp->flags |= ESP_FLAG_USE_FIFO;
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/*
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* Enable CONFIG2_FENAB to allow for large DMA transfers
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*/
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if (am53c974_fenab)
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esp->config2 |= ESP_CONFIG2_FENAB;
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pep->esp = esp;
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if (pci_request_regions(pdev, DRV_MODULE_NAME)) {
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dev_printk(KERN_ERR, &pdev->dev,
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"pci memory selection failed\n");
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goto fail_priv_alloc;
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}
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esp->regs = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
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if (!esp->regs) {
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dev_printk(KERN_ERR, &pdev->dev, "pci I/O map failed\n");
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err = -EINVAL;
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goto fail_release_regions;
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}
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esp->dma_regs = esp->regs;
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pci_set_master(pdev);
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esp->command_block = dma_alloc_coherent(&pdev->dev, 16,
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&esp->command_block_dma, GFP_KERNEL);
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if (!esp->command_block) {
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dev_printk(KERN_ERR, &pdev->dev,
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"failed to allocate command block\n");
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err = -ENOMEM;
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goto fail_unmap_regs;
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}
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pci_set_drvdata(pdev, pep);
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err = request_irq(pdev->irq, scsi_esp_intr, IRQF_SHARED,
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DRV_MODULE_NAME, esp);
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if (err < 0) {
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dev_printk(KERN_ERR, &pdev->dev, "failed to register IRQ\n");
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goto fail_unmap_command_block;
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}
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esp->scsi_id = 7;
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dc390_check_eeprom(esp);
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shost->this_id = esp->scsi_id;
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shost->max_id = 8;
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shost->irq = pdev->irq;
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shost->io_port = pci_resource_start(pdev, 0);
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shost->n_io_port = pci_resource_len(pdev, 0);
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shost->unique_id = shost->io_port;
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esp->scsi_id_mask = (1 << esp->scsi_id);
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/* Assume 40MHz clock */
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esp->cfreq = 40000000;
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err = scsi_esp_register(esp);
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if (err)
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goto fail_free_irq;
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return 0;
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fail_free_irq:
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free_irq(pdev->irq, esp);
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fail_unmap_command_block:
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pci_set_drvdata(pdev, NULL);
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dma_free_coherent(&pdev->dev, 16, esp->command_block,
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esp->command_block_dma);
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fail_unmap_regs:
|
|
pci_iounmap(pdev, esp->regs);
|
|
fail_release_regions:
|
|
pci_release_regions(pdev);
|
|
fail_priv_alloc:
|
|
kfree(pep);
|
|
fail_host_alloc:
|
|
scsi_host_put(shost);
|
|
fail_disable_device:
|
|
pci_disable_device(pdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void pci_esp_remove_one(struct pci_dev *pdev)
|
|
{
|
|
struct pci_esp_priv *pep = pci_get_drvdata(pdev);
|
|
struct esp *esp = pep->esp;
|
|
|
|
scsi_esp_unregister(esp);
|
|
free_irq(pdev->irq, esp);
|
|
pci_set_drvdata(pdev, NULL);
|
|
dma_free_coherent(&pdev->dev, 16, esp->command_block,
|
|
esp->command_block_dma);
|
|
pci_iounmap(pdev, esp->regs);
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
kfree(pep);
|
|
|
|
scsi_host_put(esp->host);
|
|
}
|
|
|
|
static struct pci_device_id am53c974_pci_tbl[] = {
|
|
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_SCSI,
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, am53c974_pci_tbl);
|
|
|
|
static struct pci_driver am53c974_driver = {
|
|
.name = DRV_MODULE_NAME,
|
|
.id_table = am53c974_pci_tbl,
|
|
.probe = pci_esp_probe_one,
|
|
.remove = pci_esp_remove_one,
|
|
};
|
|
|
|
module_pci_driver(am53c974_driver);
|
|
|
|
MODULE_DESCRIPTION("AM53C974 SCSI driver");
|
|
MODULE_AUTHOR("Hannes Reinecke <hare@suse.de>");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION(DRV_MODULE_VERSION);
|
|
MODULE_ALIAS("tmscsim");
|
|
|
|
module_param(am53c974_debug, bool, 0644);
|
|
MODULE_PARM_DESC(am53c974_debug, "Enable debugging");
|
|
|
|
module_param(am53c974_fenab, bool, 0444);
|
|
MODULE_PARM_DESC(am53c974_fenab, "Enable 24-bit DMA transfer sizes");
|