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3ccfebedd8
Allow PowerPC to skip the full memory barrier in switch_mm(), and only issue the barrier when scheduling into a task belonging to a process that has registered to use expedited private. Threads targeting the same VM but which belong to different thread groups is a tricky case. It has a few consequences: It turns out that we cannot rely on get_nr_threads(p) to count the number of threads using a VM. We can use (atomic_read(&mm->mm_users) == 1 && get_nr_threads(p) == 1) instead to skip the synchronize_sched() for cases where the VM only has a single user, and that user only has a single thread. It also turns out that we cannot use for_each_thread() to set thread flags in all threads using a VM, as it only iterates on the thread group. Therefore, test the membarrier state variable directly rather than relying on thread flags. This means membarrier_register_private_expedited() needs to set the MEMBARRIER_STATE_PRIVATE_EXPEDITED flag, issue synchronize_sched(), and only then set MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY which allows private expedited membarrier commands to succeed. membarrier_arch_switch_mm() now tests for the MEMBARRIER_STATE_PRIVATE_EXPEDITED flag. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alan Stern <stern@rowland.harvard.edu> Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: Andrea Parri <parri.andrea@gmail.com> Cc: Andrew Hunter <ahh@google.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Avi Kivity <avi@scylladb.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Dave Watson <davejwatson@fb.com> Cc: David Sehr <sehr@google.com> Cc: Greg Hackmann <ghackmann@google.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Maged Michael <maged.michael@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-api@vger.kernel.org Cc: linux-arch@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Link: http://lkml.kernel.org/r/20180129202020.8515-3-mathieu.desnoyers@efficios.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
97 lines
2.6 KiB
C
97 lines
2.6 KiB
C
/*
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* Common implementation of switch_mm_irqs_off
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*
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* Copyright IBM Corp. 2017
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/mm.h>
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#include <linux/cpu.h>
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#include <linux/sched/mm.h>
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#include <asm/mmu_context.h>
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#if defined(CONFIG_PPC32)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 32-bit keeps track of the current PGDIR in the thread struct */
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tsk->thread.pgdir = mm->pgd;
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}
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#elif defined(CONFIG_PPC_BOOK3E_64)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 64-bit Book3E keeps track of current PGD in the PACA */
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get_paca()->pgd = mm->pgd;
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}
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#else
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm) { }
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#endif
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void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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bool new_on_cpu = false;
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/* Mark this context has been used on the new CPU */
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if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
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inc_mm_active_cpus(next);
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/*
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* This full barrier orders the store to the cpumask above vs
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* a subsequent operation which allows this CPU to begin loading
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* translations for next.
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*
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* When using the radix MMU that operation is the load of the
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* MMU context id, which is then moved to SPRN_PID.
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*
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* For the hash MMU it is either the first load from slb_cache
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* in switch_slb(), and/or the store of paca->mm_ctx_id in
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* copy_mm_to_paca().
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*
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* On the read side the barrier is in pte_xchg(), which orders
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* the store to the PTE vs the load of mm_cpumask.
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*
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* This full barrier is needed by membarrier when switching
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* between processes after store to rq->curr, before user-space
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* memory accesses.
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*/
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smp_mb();
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new_on_cpu = true;
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}
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/* Some subarchs need to track the PGD elsewhere */
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switch_mm_pgdir(tsk, next);
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/* Nothing else to do if we aren't actually switching */
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if (prev == next)
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return;
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/*
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* We must stop all altivec streams before changing the HW
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* context
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*/
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile ("dssall");
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if (new_on_cpu)
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radix_kvm_prefetch_workaround(next);
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else
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membarrier_arch_switch_mm(prev, next, tsk);
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/*
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* The actual HW switching method differs between the various
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* sub architectures. Out of line for now
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*/
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switch_mmu_context(prev, next, tsk);
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}
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