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![Viresh Kumar](/assets/img/avatar_default.png)
This patch moves shirq interrupt controllers driver and header file out of plat-spear directory. It is moved to drivers/irqchip/ directory. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
316 lines
7.2 KiB
C
316 lines
7.2 KiB
C
/*
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* SPEAr platform shared irq layer source file
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*
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* Copyright (C) 2009-2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* Copyright (C) 2012 ST Microelectronics
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* Shiraz Hashim <shiraz.hashim@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/spear-shirq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/spinlock.h>
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static DEFINE_SPINLOCK(lock);
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/* spear300 shared irq registers offsets and masks */
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#define SPEAR300_INT_ENB_MASK_REG 0x54
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#define SPEAR300_INT_STS_MASK_REG 0x58
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static struct spear_shirq spear300_shirq_ras1 = {
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.irq_nr = 9,
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.irq_bit_off = 0,
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.regs = {
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.enb_reg = SPEAR300_INT_ENB_MASK_REG,
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.status_reg = SPEAR300_INT_STS_MASK_REG,
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.clear_reg = -1,
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},
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};
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static struct spear_shirq *spear300_shirq_blocks[] = {
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&spear300_shirq_ras1,
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};
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/* spear310 shared irq registers offsets and masks */
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#define SPEAR310_INT_STS_MASK_REG 0x04
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static struct spear_shirq spear310_shirq_ras1 = {
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.irq_nr = 8,
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.irq_bit_off = 0,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.clear_reg = -1,
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},
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};
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static struct spear_shirq spear310_shirq_ras2 = {
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.irq_nr = 5,
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.irq_bit_off = 8,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.clear_reg = -1,
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},
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};
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static struct spear_shirq spear310_shirq_ras3 = {
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.irq_nr = 1,
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.irq_bit_off = 13,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.clear_reg = -1,
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},
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};
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static struct spear_shirq spear310_shirq_intrcomm_ras = {
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.irq_nr = 3,
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.irq_bit_off = 14,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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.clear_reg = -1,
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},
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};
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static struct spear_shirq *spear310_shirq_blocks[] = {
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&spear310_shirq_ras1,
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&spear310_shirq_ras2,
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&spear310_shirq_ras3,
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&spear310_shirq_intrcomm_ras,
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};
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/* spear320 shared irq registers offsets and masks */
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#define SPEAR320_INT_STS_MASK_REG 0x04
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#define SPEAR320_INT_CLR_MASK_REG 0x04
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#define SPEAR320_INT_ENB_MASK_REG 0x08
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static struct spear_shirq spear320_shirq_ras1 = {
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.irq_nr = 3,
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.irq_bit_off = 7,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct spear_shirq spear320_shirq_ras2 = {
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.irq_nr = 1,
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.irq_bit_off = 10,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct spear_shirq spear320_shirq_ras3 = {
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.irq_nr = 3,
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.irq_bit_off = 0,
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.invalid_irq = 1,
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.regs = {
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.enb_reg = SPEAR320_INT_ENB_MASK_REG,
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.reset_to_enb = 1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct spear_shirq spear320_shirq_intrcomm_ras = {
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.irq_nr = 11,
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.irq_bit_off = 11,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct spear_shirq *spear320_shirq_blocks[] = {
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&spear320_shirq_ras3,
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&spear320_shirq_ras1,
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&spear320_shirq_ras2,
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&spear320_shirq_intrcomm_ras,
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};
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static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
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{
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struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
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u32 val, offset = d->irq - shirq->irq_base;
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unsigned long flags;
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if (shirq->regs.enb_reg == -1)
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return;
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spin_lock_irqsave(&lock, flags);
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val = readl(shirq->base + shirq->regs.enb_reg);
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if (mask ^ shirq->regs.reset_to_enb)
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val &= ~(0x1 << shirq->irq_bit_off << offset);
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else
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val |= 0x1 << shirq->irq_bit_off << offset;
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writel(val, shirq->base + shirq->regs.enb_reg);
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spin_unlock_irqrestore(&lock, flags);
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}
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static void shirq_irq_mask(struct irq_data *d)
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{
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shirq_irq_mask_unmask(d, 1);
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}
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static void shirq_irq_unmask(struct irq_data *d)
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{
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shirq_irq_mask_unmask(d, 0);
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}
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static struct irq_chip shirq_chip = {
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.name = "spear-shirq",
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.irq_ack = shirq_irq_mask,
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.irq_mask = shirq_irq_mask,
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.irq_unmask = shirq_irq_unmask,
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};
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static void shirq_handler(unsigned irq, struct irq_desc *desc)
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{
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u32 i, j, val, mask, tmp;
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struct irq_chip *chip;
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struct spear_shirq *shirq = irq_get_handler_data(irq);
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chip = irq_get_chip(irq);
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chip->irq_ack(&desc->irq_data);
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mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
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while ((val = readl(shirq->base + shirq->regs.status_reg) &
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mask)) {
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val >>= shirq->irq_bit_off;
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for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
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if (!(j & val))
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continue;
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generic_handle_irq(shirq->irq_base + i);
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/* clear interrupt */
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if (shirq->regs.clear_reg == -1)
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continue;
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tmp = readl(shirq->base + shirq->regs.clear_reg);
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if (shirq->regs.reset_to_clear)
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tmp &= ~(j << shirq->irq_bit_off);
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else
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tmp |= (j << shirq->irq_bit_off);
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writel(tmp, shirq->base + shirq->regs.clear_reg);
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}
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}
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chip->irq_unmask(&desc->irq_data);
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}
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static void __init spear_shirq_register(struct spear_shirq *shirq)
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{
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int i;
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if (shirq->invalid_irq)
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return;
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irq_set_chained_handler(shirq->irq, shirq_handler);
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for (i = 0; i < shirq->irq_nr; i++) {
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irq_set_chip_and_handler(shirq->irq_base + i,
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&shirq_chip, handle_simple_irq);
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set_irq_flags(shirq->irq_base + i, IRQF_VALID);
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irq_set_chip_data(shirq->irq_base + i, shirq);
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}
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irq_set_handler_data(shirq->irq, shirq);
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}
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static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
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struct device_node *np)
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{
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int i, irq_base, hwirq = 0, irq_nr = 0;
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static struct irq_domain *shirq_domain;
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void __iomem *base;
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("%s: failed to map shirq registers\n", __func__);
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return -ENXIO;
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}
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for (i = 0; i < block_nr; i++)
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irq_nr += shirq_blocks[i]->irq_nr;
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irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
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if (IS_ERR_VALUE(irq_base)) {
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pr_err("%s: irq desc alloc failed\n", __func__);
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goto err_unmap;
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}
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shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (WARN_ON(!shirq_domain)) {
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pr_warn("%s: irq domain init failed\n", __func__);
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goto err_free_desc;
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}
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for (i = 0; i < block_nr; i++) {
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shirq_blocks[i]->base = base;
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shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
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hwirq);
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shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
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spear_shirq_register(shirq_blocks[i]);
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hwirq += shirq_blocks[i]->irq_nr;
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}
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return 0;
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err_free_desc:
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irq_free_descs(irq_base, irq_nr);
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err_unmap:
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iounmap(base);
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return -ENXIO;
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}
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int __init spear300_shirq_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return shirq_init(spear300_shirq_blocks,
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ARRAY_SIZE(spear300_shirq_blocks), np);
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}
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int __init spear310_shirq_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return shirq_init(spear310_shirq_blocks,
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ARRAY_SIZE(spear310_shirq_blocks), np);
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}
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int __init spear320_shirq_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return shirq_init(spear320_shirq_blocks,
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ARRAY_SIZE(spear320_shirq_blocks), np);
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}
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