mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 21:57:43 +00:00
4d9b86eb38
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmH1KTEQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD11PfD/4tFiY40inEHZIjWSrIB/D3RZhVzslSeT2d
bABVtync3w0gTQZpT/E06XtSGrxLFh0hEa9ZJp94whiSFQ8xO8ziJONdp7T0zkzM
cJNufT5bsROGIhlnqX7FjZVyuqTKla1Uch5BwLbC1+0jeNFeic6tUXyWgk+ds0Dh
mmyKNNNpPW0kU5PTmk2rHxK171JCS7id4mpGCujqvMaBPB4RXHQJ/qjV/3e0QvmY
eReX+QVeMyeGg0UcFvxaVVT1Nw5TgFRzA9cOaIJ/JXbi/Jp7PagkvB6ZHk7smR7V
dxnPyQoASx41NPNRifVLUFmsGfrBzMO22JYHEzu0P7effbMLxDZoTU1lsBXWLDad
q7zWf9OpEK3hEwVM7vSwPZpLH14P7MqKvaDYEW1OdbC2zW3wT5McodUhCAdHsCxx
0iCmWxoOV8JyP8MbmW2I5o5Nw7lUW8hKg5KGYnUK6DLFDCkn8OP1XA+pnwr50H4t
FqGjKdLAjddId8KIEI+FO5O59kpPm082B71rpR/97D4nOaPOWfvv9NDRcwXbmkOv
nUPM/By6XwXo8NfdU/rcwJDGwDv1fe+nNVDU0aKXNLVhpGO3dkR6l14VQsQrsH2E
Dd4Hmio3HBClLGREkCbl0+5H9+a+ACOQ11XJlXmmHJkwb5SzmM2CYQRNxE6NxArd
3s63FKVA1w==
=aFcq
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmIY5fwACgkQmmx57+YA
GNn37xAAiwrsEdyqDFerNB/JVUJRLlw93TY6PojPnsj60x98UfeJbcgPeEUjYNPk
hl3HIOtpyrHom1UmqJXFROKSNq+S/rwfOJS67uwtYBgM7YwU3KCHVIeJbT1Pzwzm
dE80TSX1nolTFctCsI90mQzN72tRJbQZhvz8vP7FlkOLDe7YFIjy1j5gGify+d4J
M1YnMRVSCEA4Ba7bggQL7RWfhLzwkT4lEYLRkSGpH0kGmnW/2s+4iCxDMTqfjufF
NYP+3ctDmXfReDInkvdVHHT/F5f04C0r6JO+S7+Hvo0SJAE1zPAsNcST/dkE9hsQ
0W8VP3+EviU/k9Gmd3fPBfzX0zWzeEIaQwn3i9XVkIE4QGgXcwNOTksWgBAqyRj7
Bc6qNLmFK79dLIavRp1jmZzdDpK8yLHrVhcQjppmBBHcjW6BdBf7LN6ZYjr65qlo
ecITWLzkVLOL7iTGlLvgU1NYKUKpOJ98w2a86DbX3iAg1m1o0i0pABGCQurpUdKJ
od1y8o+xMT3+zEyK+K/Rx+ugXny1nm08qbkaApJu0yKaS5c0UhTQWPqrqvZfe+Jp
Am2KPG4EM+dDaUOj5MSItt4DeyBWQqmdLGiPJbxrVK9rmYW7CO3CotwOJU2E3St7
0dv7wRkfmuwbEt9BF9ITuNjLUXM60eR94IJV345QVxi6lVYg6ho=
=CjdH
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung pinctrl DTS and driver changes for v5.18
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
* tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9
ARM: dts: s5pv210: align pinctrl with dtschema
ARM: dts: s3c64xx: align pinctrl with dtschema
ARM: dts: s3c24xx: align pinctrl with dtschema
arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9
arm64: dts: exynos: align pinctrl with dtschema in Exynos7
arm64: dts: exynos: align pinctrl with dtschema in Exynos5433
ARM: dts: exynos: align pinctrl with dtschema in Exynos542x/5800
ARM: dts: exynos: align pinctrl with dtschema in Exynos5410
ARM: dts: exynos: align pinctrl with dtschema in Exynos5260
ARM: dts: exynos: align pinctrl with dtschema in Exynos5250
ARM: dts: exynos: align pinctrl with dtschema in Exynos4412
ARM: dts: exynos: align pinctrl with dtschema in Exynos4210
ARM: dts: exynos: align pinctrl with dtschema in Exynos3250
ARM: dts: s3c64xx: drop unneeded pinctrl wake-up interrupt mapping
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pi
ARM: dts: exynos: override pins by label in Peach Pi
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pit
ARM: dts: exynos: override pins by label in Peach Pit
ARM: dts: exynos: simplify PMIC DVS pin configuration in Odroid XU
...
Link: https://lore.kernel.org/r/20220129115352.13274-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
837 lines
18 KiB
Text
837 lines
18 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's Exynos5420 based Arndale Octa board device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*/
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/dts-v1/;
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#include "exynos5420.dtsi"
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#include "exynos5420-cpus.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/clock/samsung,s2mps11.h>
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/ {
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model = "Insignal Arndale Octa evaluation board based on Exynos5420";
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compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
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memory@20000000 {
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device_type = "memory";
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reg = <0x20000000 0x80000000>;
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};
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chosen {
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stdout-path = "serial3:115200n8";
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};
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firmware@2073000 {
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compatible = "samsung,secure-firmware";
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reg = <0x02073000 0x1000>;
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};
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fixed-rate-clocks {
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oscclk {
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compatible = "samsung,exynos5420-oscclk";
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clock-frequency = <24000000>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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wakeup {
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label = "SW-TACT1";
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gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WAKEUP>;
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wakeup-source;
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};
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};
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};
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&adc {
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vdd-supply = <&ldo4_reg>;
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status = "okay";
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};
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&cci {
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status = "disabled";
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};
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&cpu0 {
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cpu-supply = <&buck2_reg>;
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};
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&cpu4 {
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cpu-supply = <&buck6_reg>;
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};
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&cpu0_thermal {
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trips {
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cpu0_alert0: cpu-alert-0 {
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temperature = <60000>; /* millicelsius */
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hysteresis = <5000>; /* millicelsius */
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type = "passive";
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};
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cpu0_alert1: cpu-alert-1 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu0_alert2: cpu-alert-2 {
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temperature = <110000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu0_crit0: cpu-crit-0 {
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temperature = <120000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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/*
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* Reduce the CPU speed by 2 steps, down to: 1600 MHz
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* and 1100 MHz.
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*/
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map0 {
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trip = <&cpu0_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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/*
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* Reduce the CPU speed down to 1200 MHz big (6 steps)
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* and 800 MHz LITTLE (5 steps).
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*/
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map1 {
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trip = <&cpu0_alert1>;
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cooling-device = <&cpu0 3 6>,
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<&cpu1 3 6>,
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<&cpu2 3 6>,
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<&cpu3 3 6>,
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<&cpu4 3 5>,
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<&cpu5 3 5>,
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<&cpu6 3 5>,
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<&cpu7 3 5>;
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};
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/*
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* Reduce the CPU speed as much as possible, down to 700 MHz
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* big (11 steps) and 600 MHz LITTLE (7 steps).
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*/
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map2 {
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trip = <&cpu0_alert2>;
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cooling-device = <&cpu0 6 11>,
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<&cpu1 6 11>,
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<&cpu2 6 11>,
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<&cpu3 6 11>,
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<&cpu4 5 7>,
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<&cpu5 5 7>,
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<&cpu6 5 7>,
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<&cpu7 5 7>;
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};
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};
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};
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&cpu1_thermal {
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trips {
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cpu1_alert0: cpu-alert-0 {
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temperature = <60000>; /* millicelsius */
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hysteresis = <5000>; /* millicelsius */
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type = "passive";
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};
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cpu1_alert1: cpu-alert-1 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu1_alert2: cpu-alert-2 {
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temperature = <110000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu1_crit0: cpu-crit-0 {
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temperature = <120000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu1_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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map1 {
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trip = <&cpu1_alert1>;
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cooling-device = <&cpu0 3 6>,
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<&cpu1 3 6>,
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<&cpu2 3 6>,
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<&cpu3 3 6>,
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<&cpu4 3 5>,
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<&cpu5 3 5>,
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<&cpu6 3 5>,
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<&cpu7 3 5>;
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};
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map2 {
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trip = <&cpu1_alert2>;
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cooling-device = <&cpu0 6 11>,
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<&cpu1 6 11>,
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<&cpu2 6 11>,
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<&cpu3 6 11>,
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<&cpu4 5 7>,
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<&cpu5 5 7>,
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<&cpu6 5 7>,
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<&cpu7 5 7>;
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};
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};
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};
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&cpu2_thermal {
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trips {
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cpu2_alert0: cpu-alert-0 {
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temperature = <60000>; /* millicelsius */
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hysteresis = <5000>; /* millicelsius */
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type = "passive";
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};
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cpu2_alert1: cpu-alert-1 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu2_alert2: cpu-alert-2 {
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temperature = <110000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu2_crit0: cpu-crit-0 {
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temperature = <120000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu2_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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map1 {
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trip = <&cpu2_alert1>;
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cooling-device = <&cpu0 3 6>,
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<&cpu1 3 6>,
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<&cpu2 3 6>,
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<&cpu3 3 6>,
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<&cpu4 3 5>,
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<&cpu5 3 5>,
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<&cpu6 3 5>,
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<&cpu7 3 5>;
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};
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map2 {
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trip = <&cpu2_alert2>;
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cooling-device = <&cpu0 6 11>,
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<&cpu1 6 11>,
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<&cpu2 6 11>,
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<&cpu3 6 11>,
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<&cpu4 6 7>,
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<&cpu5 6 7>,
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<&cpu6 6 7>,
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<&cpu7 6 7>;
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};
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};
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};
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&cpu3_thermal {
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trips {
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cpu3_alert0: cpu-alert-0 {
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temperature = <60000>; /* millicelsius */
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hysteresis = <5000>; /* millicelsius */
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type = "passive";
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};
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cpu3_alert1: cpu-alert-1 {
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temperature = <80000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu3_alert2: cpu-alert-2 {
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temperature = <110000>; /* millicelsius */
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hysteresis = <10000>; /* millicelsius */
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type = "passive";
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};
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cpu3_crit0: cpu-crit-0 {
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temperature = <120000>; /* millicelsius */
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hysteresis = <0>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu3_alert0>;
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cooling-device = <&cpu0 0 2>,
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<&cpu1 0 2>,
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<&cpu2 0 2>,
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<&cpu3 0 2>,
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<&cpu4 0 2>,
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<&cpu5 0 2>,
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<&cpu6 0 2>,
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<&cpu7 0 2>;
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};
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map1 {
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trip = <&cpu3_alert1>;
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cooling-device = <&cpu0 3 6>,
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<&cpu1 3 6>,
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<&cpu2 3 6>,
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<&cpu3 3 6>,
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<&cpu4 3 5>,
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<&cpu5 3 5>,
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<&cpu6 3 5>,
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<&cpu7 3 5>;
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};
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map2 {
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trip = <&cpu3_alert2>;
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cooling-device = <&cpu0 6 11>,
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<&cpu1 6 11>,
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<&cpu2 6 11>,
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<&cpu3 6 11>,
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<&cpu4 5 7>,
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<&cpu5 5 7>,
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<&cpu6 5 7>,
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<&cpu7 5 7>;
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};
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};
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};
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&hdmi {
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hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
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vdd_osc-supply = <&ldo7_reg>;
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vdd_pll-supply = <&ldo6_reg>;
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vdd-supply = <&ldo6_reg>;
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ddc = <&i2c_2>;
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status = "okay";
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};
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&hsi2c_4 {
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status = "okay";
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pmic@66 {
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compatible = "samsung,s2mps11-pmic";
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reg = <0x66>;
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interrupt-parent = <&gpx3>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&s2mps11_irq>;
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wakeup-source;
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s2mps11_osc: clocks {
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compatible = "samsung,s2mps11-clk";
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#clock-cells = <1>;
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clock-output-names = "s2mps11_ap",
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"s2mps11_cp", "s2mps11_bt";
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};
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regulators {
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ldo1_reg: LDO1 {
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regulator-name = "PVDD_ALIVE_1V0";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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ldo2_reg: LDO2 {
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regulator-name = "PVDD_APIO_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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ldo3_reg: LDO3 {
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regulator-name = "PVDD_APIO_MMCON_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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/*
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* Must be always on, even though there is
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* a consumer (mmc_0). Otherwise the board
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* does not reboot with vendor U-Boot
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* (Linaro for Arndale Octa, v2012.07).
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*/
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regulator-always-on;
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
|
|
|
|
ldo4_reg: LDO4 {
|
|
regulator-name = "PVDD_ADC_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo5_reg: LDO5 {
|
|
regulator-name = "PVDD_PLL_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo6_reg: LDO6 {
|
|
regulator-name = "PVDD_ANAIP_1V0";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
};
|
|
|
|
ldo7_reg: LDO7 {
|
|
regulator-name = "PVDD_ANAIP_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo8_reg: LDO8 {
|
|
regulator-name = "PVDD_ABB_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo9_reg: LDO9 {
|
|
regulator-name = "PVDD_USB_3V3";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo10_reg: LDO10 {
|
|
regulator-name = "PVDD_PRE_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo11_reg: LDO11 {
|
|
regulator-name = "PVDD_USB_1V0";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo12_reg: LDO12 {
|
|
regulator-name = "PVDD_HSIC_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo13_reg: LDO13 {
|
|
regulator-name = "PVDD_APIO_MMCOFF_2V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo14_reg: LDO14 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO14";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo15_reg: LDO15 {
|
|
regulator-name = "PVDD_PERI_2V8";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
regulator-state-mem {
|
|
regulator-on-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo16_reg: LDO16 {
|
|
regulator-name = "PVDD_PERI_3V3";
|
|
regulator-min-microvolt = <2200000>;
|
|
regulator-max-microvolt = <2200000>;
|
|
|
|
regulator-state-mem {
|
|
regulator-on-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo17_reg: LDO17 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO17";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo18_reg: LDO18 {
|
|
regulator-name = "PVDD_EMMC_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
/*
|
|
* Must stay in "off" mode during shutdown for
|
|
* proper eMMC reset. The "off" mode is in
|
|
* fact controlled by LDO18EN. The eMMC does
|
|
* not have reset pin connected so the reset
|
|
* will be triggered by falling edge of
|
|
* LDO18EN.
|
|
*/
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo19_reg: LDO19 {
|
|
regulator-name = "PVDD_TFLASH_2V8";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo20_reg: LDO20 {
|
|
regulator-name = "PVDD_BTWIFI_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo21_reg: LDO21 {
|
|
regulator-name = "PVDD_CAM1IO_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo22_reg: LDO22 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO22";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <2375000>;
|
|
};
|
|
|
|
ldo23_reg: LDO23 {
|
|
regulator-name = "PVDD_MIFS_1V1";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-on-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo24_reg: LDO24 {
|
|
regulator-name = "PVDD_CAM1_AVDD_2V8";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
regulator-state-mem {
|
|
regulator-on-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo25_reg: LDO25 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO25";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo26_reg: LDO26 {
|
|
regulator-name = "PVDD_CAM0_AF_2V8";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
};
|
|
|
|
ldo27_reg: LDO27 {
|
|
regulator-name = "PVDD_G3DS_1V0";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-on-in-suspend;
|
|
};
|
|
};
|
|
|
|
ldo28_reg: LDO28 {
|
|
regulator-name = "PVDD_TSP_3V3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
ldo29_reg: LDO29 {
|
|
regulator-name = "PVDD_AUDIO_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo30_reg: LDO30 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO30";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo31_reg: LDO31 {
|
|
regulator-name = "PVDD_PERI_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo32_reg: LDO32 {
|
|
regulator-name = "PVDD_LCD_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo33_reg: LDO33 {
|
|
regulator-name = "PVDD_CAM0IO_1V8";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo34_reg: LDO34 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO34";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo35_reg: LDO35 {
|
|
regulator-name = "PVDD_CAM0_DVDD_1V2";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
};
|
|
|
|
ldo36_reg: LDO36 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO36";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo37_reg: LDO37 {
|
|
/* Unused */
|
|
regulator-name = "PVDD_LDO37";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <3950000>;
|
|
};
|
|
|
|
ldo38_reg: LDO38 {
|
|
regulator-name = "PVDD_CAM0_AVDD_2V8";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
};
|
|
|
|
buck1_reg: BUCK1 {
|
|
regulator-name = "PVDD_MIF_1V1";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1300000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
buck2_reg: BUCK2 {
|
|
regulator-name = "PVDD_ARM_1V0";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1500000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
buck3_reg: BUCK3 {
|
|
regulator-name = "PVDD_INT_1V0";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
buck4_reg: BUCK4 {
|
|
regulator-name = "PVDD_G3D_1V0";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
buck5_reg: BUCK5 {
|
|
regulator-name = "PVDD_LPDDR3_1V2";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck6_reg: BUCK6 {
|
|
regulator-name = "PVDD_KFC_1V0";
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1500000>;
|
|
regulator-always-on;
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
|
|
buck7_reg: BUCK7 {
|
|
regulator-name = "VIN_LLDO_1V4";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1500000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck8_reg: BUCK8 {
|
|
regulator-name = "VIN_MLDO_2V0";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <2100000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck9_reg: BUCK9 {
|
|
regulator-name = "VIN_HLDO_3V5";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3500000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
buck10_reg: BUCK10 {
|
|
regulator-name = "PVDD_EMMCF_2V8";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
/*
|
|
* Must stay in "off" mode during shutdown for
|
|
* proper eMMC reset. The "off" mode is in
|
|
* fact controlled by BUCK10EN. The eMMC does
|
|
* not have reset pin connected so the reset
|
|
* will be triggered by falling edge of
|
|
* BUCK10EN.
|
|
*/
|
|
|
|
regulator-state-mem {
|
|
regulator-off-in-suspend;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c_2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&mixer {
|
|
status = "okay";
|
|
};
|
|
|
|
&mmc_0 {
|
|
status = "okay";
|
|
non-removable;
|
|
card-detect-delay = <200>;
|
|
samsung,dw-mshc-ciu-div = <3>;
|
|
samsung,dw-mshc-sdr-timing = <0 4>;
|
|
samsung,dw-mshc-ddr-timing = <0 2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
|
|
vmmc-supply = <&ldo18_reg>;
|
|
vqmmc-supply = <&ldo3_reg>;
|
|
bus-width = <8>;
|
|
cap-mmc-highspeed;
|
|
mmc-hs200-1_8v;
|
|
};
|
|
|
|
&mmc_2 {
|
|
status = "okay";
|
|
card-detect-delay = <200>;
|
|
samsung,dw-mshc-ciu-div = <3>;
|
|
samsung,dw-mshc-sdr-timing = <0 4>;
|
|
samsung,dw-mshc-ddr-timing = <0 2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
|
|
vmmc-supply = <&ldo19_reg>;
|
|
vqmmc-supply = <&ldo13_reg>;
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
sd-uhs-sdr50;
|
|
sd-uhs-sdr104;
|
|
sd-uhs-ddr50;
|
|
};
|
|
|
|
&pinctrl_0 {
|
|
s2mps11_irq: s2mps11-irq-pins {
|
|
samsung,pins = "gpx3-2";
|
|
samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
|
|
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
|
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
|
|
clock-names = "rtc", "rtc_src";
|
|
};
|
|
|
|
&usbdrd_dwc3_1 {
|
|
dr_mode = "host";
|
|
};
|
|
|
|
&usbdrd3_0 {
|
|
vdd10-supply = <&ldo11_reg>;
|
|
vdd33-supply = <&ldo9_reg>;
|
|
};
|
|
|
|
&usbdrd3_1 {
|
|
vdd10-supply = <&ldo11_reg>;
|
|
vdd33-supply = <&ldo9_reg>;
|
|
};
|