mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
SoC platform changes. Main theme this merge window: - The Netx platform (Netx 100/500) platform is removed by Linus Walleij-- the SoC doesn't have active maintainers with hardware, and in discussions with the vendor the agreement was that it's OK to remove. - Russell King has a series of patches that cleans up and refactors SA1101 and RiscPC support. -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yKOgPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3SNEP/iJsMeeunX0P7Ym3zNFjykhspkkUmo7sEKuz NBcexnQpkm+OLgjfwT7j3kXvOs4mzMzH56J6h7dEDSHbQP1MDIgpMw6OEzMMsQTV XL1AWz1IO7Sq/mG17daPs9c75o6NYQ7pSEd/ncbjKuJQOpGsi4DyrVrhk9WdzYl2 hcs4XOzOMZgDTsXHVdWkfpHazpWxEXPCD7v5bt6ueU0YnT3csUbzOTTvw+55JxRV fYz0lg4wTMRYMQMOejpx1HXwdmbVOHLUYkCxcLUaVqMnm88q/IddJVklBbPGWAU5 Z4gFpL+FxcFhEZtu28CoubPYzf/mHDk8Ry2UWwBiRwiGoKfblomI1fpnbyrX53aE lpO5p7MfOVVV2WNxpbUND+ilbgKOREfRHd314GLPUjwudp2sTuDRZ1GAbt3JwsIM L1HesyjCtb6itCSwGsmmGsX2Wvu+WT7slpsYwHs2qklE/X1zQq0R4Jf2xUNpwqPb FqGZAtc6CCQtyF/Mcpp6OQd+cV0tgQVIw7teKol/xR1dSzN/+1zO1J9UHk9/dWUU sb5lGa/AtBrIbWxS1qLuA5bgyDqxXYDZi0y/Bu1qMHYebRW37z9kvomtzBiMNX2o SAxvr9iGPlTxTjGjRCyBVFmsbCMYLabNoL9tuuXvo+DnjFoOilTef+qePOv7ZYZX kwUyS2eu =FX6e -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC platform updates from Olof Johansson: "SoC platform changes. Main theme this merge window: - The Netx platform (Netx 100/500) platform is removed by Linus Walleij-- the SoC doesn't have active maintainers with hardware, and in discussions with the vendor the agreement was that it's OK to remove. - Russell King has a series of patches that cleans up and refactors SA1101 and RiscPC support" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) ARM: stm32: use "depends on" instead of "if" after prompt ARM: sa1100: convert to common clock framework ARM: exynos: Cleanup cppcheck shifting warning ARM: pxa/lubbock: remove lubbock_set_misc_wr() from global view ARM: exynos: Only build MCPM support if used arm: add missing include platform-data/atmel.h ARM: davinci: Use GPIO lookup table for DA850 LEDs ARM: OMAP2: drop explicit assembler architecture ARM: use arch_extension directive instead of arch argument ARM: imx: Switch imx7d to imx-cpufreq-dt for speed-grading ARM: bcm: Enable PINCTRL for ARCH_BRCMSTB ARM: bcm: Enable ARCH_HAS_RESET_CONTROLLER for ARCH_BRCMSTB ARM: riscpc: enable chained scatterlist support ARM: riscpc: reduce IRQ handling code ARM: riscpc: move RiscPC assembly files from arch/arm/lib to mach-rpc ARM: riscpc: parse video information from tagged list ARM: riscpc: add ecard quirk for Atomwide 3port serial card MAINTAINERS: mvebu: Add git entry soc: ti: pm33xx: Add a print while entering RTC only mode with DDR in self-refresh ARM: OMAP2+: Make some variables static ...
169 lines
4.1 KiB
C
169 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Broadcom BCM63138 DSL SoCs SMP support code
|
|
*
|
|
* Copyright (C) 2015, Broadcom Corporation
|
|
*/
|
|
|
|
#include <linux/delay.h>
|
|
#include <linux/init.h>
|
|
#include <linux/smp.h>
|
|
#include <linux/io.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/smp_scu.h>
|
|
#include <asm/smp_plat.h>
|
|
#include <asm/vfp.h>
|
|
|
|
#include "bcm63xx_smp.h"
|
|
|
|
/* Size of mapped Cortex A9 SCU address space */
|
|
#define CORTEX_A9_SCU_SIZE 0x58
|
|
|
|
/*
|
|
* Enable the Cortex A9 Snoop Control Unit
|
|
*
|
|
* By the time this is called we already know there are multiple
|
|
* cores present. We assume we're running on a Cortex A9 processor,
|
|
* so any trouble getting the base address register or getting the
|
|
* SCU base is a problem.
|
|
*
|
|
* Return 0 if successful or an error code otherwise.
|
|
*/
|
|
static int __init scu_a9_enable(void)
|
|
{
|
|
unsigned long config_base;
|
|
void __iomem *scu_base;
|
|
unsigned int i, ncores;
|
|
|
|
if (!scu_a9_has_base()) {
|
|
pr_err("no configuration base address register!\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
/* Config base address register value is zero for uniprocessor */
|
|
config_base = scu_a9_get_base();
|
|
if (!config_base) {
|
|
pr_err("hardware reports only one core\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
|
|
if (!scu_base) {
|
|
pr_err("failed to remap config base (%lu/%u) for SCU\n",
|
|
config_base, CORTEX_A9_SCU_SIZE);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
scu_enable(scu_base);
|
|
|
|
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
|
|
|
|
if (ncores > nr_cpu_ids) {
|
|
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
|
|
ncores, nr_cpu_ids);
|
|
ncores = nr_cpu_ids;
|
|
}
|
|
|
|
/* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete
|
|
* and fully functional VFP unit that can be used, but CPU1 does not.
|
|
* Since we will not be able to trap kernel-mode NEON to force
|
|
* migration to CPU0, just do not advertise VFP support at all.
|
|
*
|
|
* This will make vfp_init bail out and do not attempt to use VFP at
|
|
* all, for kernel-mode NEON, we do not want to introduce any
|
|
* conditionals in hot-paths, so we just restrict the system to UP.
|
|
*/
|
|
#ifdef CONFIG_VFP
|
|
if (ncores > 1) {
|
|
pr_warn("SMP: secondary CPUs lack VFP unit, disabling VFP\n");
|
|
vfp_disable();
|
|
|
|
#ifdef CONFIG_KERNEL_MODE_NEON
|
|
WARN(1, "SMP: kernel-mode NEON enabled, restricting to UP\n");
|
|
ncores = 1;
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
for (i = 0; i < ncores; i++)
|
|
set_cpu_possible(i, true);
|
|
|
|
iounmap(scu_base); /* That's the last we'll need of this */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id bcm63138_bootlut_ids[] = {
|
|
{ .compatible = "brcm,bcm63138-bootlut", },
|
|
{ /* sentinel */ },
|
|
};
|
|
|
|
#define BOOTLUT_RESET_VECT 0x20
|
|
|
|
static int bcm63138_smp_boot_secondary(unsigned int cpu,
|
|
struct task_struct *idle)
|
|
{
|
|
void __iomem *bootlut_base;
|
|
struct device_node *dn;
|
|
int ret = 0;
|
|
u32 val;
|
|
|
|
dn = of_find_matching_node(NULL, bcm63138_bootlut_ids);
|
|
if (!dn) {
|
|
pr_err("SMP: unable to find bcm63138 boot LUT node\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
bootlut_base = of_iomap(dn, 0);
|
|
of_node_put(dn);
|
|
|
|
if (!bootlut_base) {
|
|
pr_err("SMP: unable to remap boot LUT base register\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Locate the secondary CPU node */
|
|
dn = of_get_cpu_node(cpu, NULL);
|
|
if (!dn) {
|
|
pr_err("SMP: failed to locate secondary CPU%d node\n", cpu);
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
/* Write the secondary init routine to the BootLUT reset vector */
|
|
val = __pa_symbol(secondary_startup);
|
|
writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
|
|
|
|
/* Power up the core, will jump straight to its reset vector when we
|
|
* return
|
|
*/
|
|
ret = bcm63xx_pmb_power_on_cpu(dn);
|
|
of_node_put(dn);
|
|
if (ret)
|
|
goto out;
|
|
out:
|
|
iounmap(bootlut_base);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __init bcm63138_smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
int ret;
|
|
|
|
ret = scu_a9_enable();
|
|
if (ret) {
|
|
pr_warn("SMP: Cortex-A9 SCU setup failed\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
static const struct smp_operations bcm63138_smp_ops __initconst = {
|
|
.smp_prepare_cpus = bcm63138_smp_prepare_cpus,
|
|
.smp_boot_secondary = bcm63138_smp_boot_secondary,
|
|
};
|
|
|
|
CPU_METHOD_OF_DECLARE(bcm63138_smp, "brcm,bcm63138", &bcm63138_smp_ops);
|