mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 09:50:04 +00:00
fb01eb3651
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
[nsekhar@ti.com: drop obsolete hawkboard.org URL completeley
fixup subject line prefix]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
216 lines
4.8 KiB
ArmAsm
216 lines
4.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* (C) Copyright 2009, Texas Instruments, Inc. https://www.ti.com/
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*/
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/* replicated define because linux/bitops.h cannot be included in assembly */
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#define BIT(nr) (1 << (nr))
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "psc.h"
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#include "ddr2.h"
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#include "clock.h"
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/* Arbitrary, hardware currently does not update PHYRDY correctly */
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#define PHYRDY_CYCLES 0x1000
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/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
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#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
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#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
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#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
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#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
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.text
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.arch armv5te
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/*
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* Move DaVinci into deep sleep state
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*
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* Note: This code is copied to internal SRAM by PM code. When the DaVinci
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* wakes up it continues execution at the point it went to sleep.
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* Register Usage:
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* r0: contains virtual base for DDR2 controller
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* r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
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* r2: contains PSC number for DDR2
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* r3: contains virtual base DDR2 PLL controller
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* r4: contains virtual address of the DEEPSLEEP register
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*/
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ENTRY(davinci_cpu_suspend)
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stmfd sp!, {r0-r12, lr} @ save registers on stack
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ldr ip, CACHE_FLUSH
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blx ip
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ldmia r0, {r0-r4}
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/*
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* Switch DDR to self-refresh mode.
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*/
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/* calculate SDRCR address */
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_SRPD_BIT
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orr ip, ip, #DDR2_LPMODEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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orr ip, ip, #DDR2_MCLKSTOPEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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mov ip, #PHYRDY_CYCLES
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1: subs ip, ip, #0x1
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bne 1b
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/* Disable DDR2 LPSC */
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mov r7, r0
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mov r0, #0x2
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bl davinci_ddr_psc_config
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mov r0, r7
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/* Disable clock to DDR PHY */
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ldr ip, [r3, #PLLDIV1]
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bic ip, ip, #PLLDIV_EN
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str ip, [r3, #PLLDIV1]
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/* Put the DDR PLL in bypass and power down */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLENSRC
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bic ip, ip, #PLLCTL_PLLEN
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str ip, [r3, #PLLCTL]
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/* Wait for PLL to switch to bypass */
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mov ip, #PLL_BYPASS_CYCLES
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2: subs ip, ip, #0x1
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bne 2b
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/* Power down the PLL */
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ldr ip, [r3, #PLLCTL]
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orr ip, ip, #PLLCTL_PLLPWRDN
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str ip, [r3, #PLLCTL]
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/* Go to deep sleep */
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ldr ip, [r4]
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orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
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/* System goes to sleep beyond after this instruction */
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str ip, [r4]
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/* Wake up from sleep */
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/* Clear sleep enable */
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ldr ip, [r4]
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bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
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str ip, [r4]
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/* initialize the DDR PLL controller */
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/* Put PLL in reset */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLRST
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str ip, [r3, #PLLCTL]
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/* Clear PLL power down */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLPWRDN
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str ip, [r3, #PLLCTL]
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mov ip, #PLL_RESET_CYCLES
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3: subs ip, ip, #0x1
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bne 3b
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/* Bring PLL out of reset */
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ldr ip, [r3, #PLLCTL]
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orr ip, ip, #PLLCTL_PLLRST
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str ip, [r3, #PLLCTL]
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/* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
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mov ip, #PLL_LOCK_CYCLES
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4: subs ip, ip, #0x1
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bne 4b
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/* Remove PLL from bypass mode */
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ldr ip, [r3, #PLLCTL]
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bic ip, ip, #PLLCTL_PLLENSRC
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orr ip, ip, #PLLCTL_PLLEN
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str ip, [r3, #PLLCTL]
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/* Start 2x clock to DDR2 */
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ldr ip, [r3, #PLLDIV1]
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orr ip, ip, #PLLDIV_EN
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str ip, [r3, #PLLDIV1]
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/* Enable VCLK */
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/* Enable DDR2 LPSC */
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mov r7, r0
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mov r0, #0x3
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bl davinci_ddr_psc_config
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mov r0, r7
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/* clear MCLKSTOPEN */
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_MCLKSTOPEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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ldr ip, [r0, #DDR2_SDRCR_OFFSET]
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bic ip, ip, #DDR2_LPMODEN_BIT
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str ip, [r0, #DDR2_SDRCR_OFFSET]
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/* Restore registers and return */
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ldmfd sp!, {r0-r12, pc}
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ENDPROC(davinci_cpu_suspend)
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/*
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* Disables or Enables DDR2 LPSC
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* Register Usage:
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* r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
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* r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
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* r2: contains PSC number for DDR2
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*/
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ENTRY(davinci_ddr_psc_config)
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/* Set next state in mdctl for DDR2 */
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mov r6, #MDCTL
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add r6, r6, r2, lsl #2
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ldr ip, [r1, r6]
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bic ip, ip, #MDSTAT_STATE_MASK
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orr ip, ip, r0
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str ip, [r1, r6]
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/* Enable the Power Domain Transition Command */
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ldr ip, [r1, #PTCMD]
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orr ip, ip, #0x1
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str ip, [r1, #PTCMD]
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/* Check for Transition Complete (PTSTAT) */
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ptstat_done:
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ldr ip, [r1, #PTSTAT]
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and ip, ip, #0x1
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cmp ip, #0x0
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bne ptstat_done
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/* Check for DDR2 clock disable completion; */
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mov r6, #MDSTAT
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add r6, r6, r2, lsl #2
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ddr2clk_stop_done:
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ldr ip, [r1, r6]
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and ip, ip, #MDSTAT_STATE_MASK
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cmp ip, r0
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bne ddr2clk_stop_done
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ret lr
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ENDPROC(davinci_ddr_psc_config)
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CACHE_FLUSH:
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#ifdef CONFIG_CPU_V6
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.word v6_flush_kern_cache_all
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#else
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.word arm926_flush_kern_cache_all
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#endif
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ENTRY(davinci_cpu_suspend_sz)
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.word . - davinci_cpu_suspend
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ENDPROC(davinci_cpu_suspend_sz)
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