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d893c4de01
This patch Enable ARM L2 cache module in Nuvoton NPCM7xx BMC by adding L2 cache parameters into NPCM7xx DT machine start structure. At patch V7 arm: npcm: add basic support for Nuvoton BMCs we got comments regarding the flags use in L2 cache module. - https://www.spinics.net/lists/arm-kernel/msg613212.html After checking again the L2 cache use in the NPCM7xx, the only L2 cache flag we need to set is L2C_AUX_CTRL_SHARED_OVERRIDE and it is done in the device tree: https://patchwork.kernel.org/patch/10063497/ L2 cache flag mask allowed all the flag option. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
22 lines
533 B
C
22 lines
533 B
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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// Copyright 2018 Google, Inc.
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/cache-l2x0.h>
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static const char *const npcm7xx_dt_match[] = {
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"nuvoton,npcm750",
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NULL
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};
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DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
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.atag_offset = 0x100,
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.dt_compat = npcm7xx_dt_match,
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.l2c_aux_val = 0x0,
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.l2c_aux_mask = ~0x0,
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MACHINE_END
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