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f18e314a6b
Commit c2ce5fb3f3 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP4, so do the same change
for OMAP4 also.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
440 lines
13 KiB
C
440 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP4 Clock domains framework
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*
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* Copyright (C) 2009-2011 Texas Instruments, Inc.
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* Copyright (C) 2009-2011 Nokia Corporation
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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* Paul Walmsley (paul@pwsan.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "cm-regbits-44xx.h"
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#include "prm44xx.h"
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#include "prcm44xx.h"
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#include "prcm_mpu44xx.h"
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/* Static Dependencies for OMAP4 Clock Domains */
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static struct clkdm_dep d2d_wkup_sleep_deps[] = {
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep ducati_wkup_sleep_deps[] = {
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_dss_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_gfx_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ .clkdm_name = "tesla_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep iss_wkup_sleep_deps[] = {
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ducati_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_dss_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep mpu_wkup_sleep_deps[] = {
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ducati_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_dss_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_gfx_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_secure_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ .clkdm_name = "tesla_clkdm" },
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{ NULL },
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};
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static struct clkdm_dep tesla_wkup_sleep_deps[] = {
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{ .clkdm_name = "abe_clkdm" },
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{ .clkdm_name = "ivahd_clkdm" },
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{ .clkdm_name = "l3_1_clkdm" },
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{ .clkdm_name = "l3_2_clkdm" },
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{ .clkdm_name = "l3_emif_clkdm" },
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{ .clkdm_name = "l3_init_clkdm" },
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{ .clkdm_name = "l4_cfg_clkdm" },
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{ .clkdm_name = "l4_per_clkdm" },
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{ .clkdm_name = "l4_wkup_clkdm" },
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{ NULL },
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};
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static struct clockdomain l4_cefuse_44xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CEFUSE_INST,
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.clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain l4_cfg_44xx_clkdm = {
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.name = "l4_cfg_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
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.dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP,
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};
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static struct clockdomain tesla_44xx_clkdm = {
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.name = "tesla_clkdm",
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.pwrdm = { .name = "tesla_pwrdm" },
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_TESLA_INST,
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.clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
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.dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
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.wkdep_srcs = tesla_wkup_sleep_deps,
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.sleepdep_srcs = tesla_wkup_sleep_deps,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain l3_gfx_44xx_clkdm = {
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.name = "l3_gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_GFX_INST,
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.clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
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.dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
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.wkdep_srcs = l3_gfx_wkup_sleep_deps,
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.sleepdep_srcs = l3_gfx_wkup_sleep_deps,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain ivahd_44xx_clkdm = {
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.name = "ivahd_clkdm",
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.pwrdm = { .name = "ivahd_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_IVAHD_INST,
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.clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
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.dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
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.wkdep_srcs = ivahd_wkup_sleep_deps,
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.sleepdep_srcs = ivahd_wkup_sleep_deps,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain l4_secure_44xx_clkdm = {
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.name = "l4_secure_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L4PER_INST,
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.clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
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.dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
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.wkdep_srcs = l4_secure_wkup_sleep_deps,
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.sleepdep_srcs = l4_secure_wkup_sleep_deps,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l4_per_44xx_clkdm = {
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.name = "l4_per_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L4PER_INST,
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.clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
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.dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain abe_44xx_clkdm = {
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.name = "abe_clkdm",
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.pwrdm = { .name = "abe_pwrdm" },
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_ABE_INST,
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.clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
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.dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain l3_instr_44xx_clkdm = {
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.name = "l3_instr_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
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};
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static struct clockdomain l3_init_44xx_clkdm = {
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.name = "l3_init_clkdm",
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.pwrdm = { .name = "l3init_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L3INIT_INST,
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.clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
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.dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
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.wkdep_srcs = l3_init_wkup_sleep_deps,
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.sleepdep_srcs = l3_init_wkup_sleep_deps,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain d2d_44xx_clkdm = {
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.name = "d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
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.wkdep_srcs = d2d_wkup_sleep_deps,
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.sleepdep_srcs = d2d_wkup_sleep_deps,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain mpu0_44xx_clkdm = {
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.name = "mpu0_clkdm",
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.pwrdm = { .name = "cpu0_pwrdm" },
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.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
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.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
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.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain mpu1_44xx_clkdm = {
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.name = "mpu1_clkdm",
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.pwrdm = { .name = "cpu1_pwrdm" },
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.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
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.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
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.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain l3_emif_44xx_clkdm = {
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.name = "l3_emif_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
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.dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain l4_ao_44xx_clkdm = {
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.name = "l4_ao_clkdm",
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.pwrdm = { .name = "always_on_core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
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.clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain ducati_44xx_clkdm = {
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.name = "ducati_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
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.dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
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.wkdep_srcs = ducati_wkup_sleep_deps,
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.sleepdep_srcs = ducati_wkup_sleep_deps,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
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static struct clockdomain mpu_44xx_clkdm = {
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.name = "mpuss_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_MPU_INST,
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.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
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.wkdep_srcs = mpu_wkup_sleep_deps,
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.sleepdep_srcs = mpu_wkup_sleep_deps,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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};
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static struct clockdomain l3_2_44xx_clkdm = {
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.name = "l3_2_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
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.dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP,
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};
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static struct clockdomain l3_1_44xx_clkdm = {
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.name = "l3_1_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
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.dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
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.flags = CLKDM_CAN_HWSUP,
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};
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static struct clockdomain iss_44xx_clkdm = {
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.name = "iss_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CAM_INST,
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.clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
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.wkdep_srcs = iss_wkup_sleep_deps,
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.sleepdep_srcs = iss_wkup_sleep_deps,
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain l3_dss_44xx_clkdm = {
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.name = "l3_dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_DSS_INST,
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.clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
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.dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
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.wkdep_srcs = l3_dss_wkup_sleep_deps,
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.sleepdep_srcs = l3_dss_wkup_sleep_deps,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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};
|
|
|
|
static struct clockdomain l4_wkup_44xx_clkdm = {
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|
.name = "l4_wkup_clkdm",
|
|
.pwrdm = { .name = "wkup_pwrdm" },
|
|
.prcm_partition = OMAP4430_PRM_PARTITION,
|
|
.cm_inst = OMAP4430_PRM_WKUP_CM_INST,
|
|
.clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
|
|
.dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
|
|
.flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
|
|
};
|
|
|
|
static struct clockdomain emu_sys_44xx_clkdm = {
|
|
.name = "emu_sys_clkdm",
|
|
.pwrdm = { .name = "emu_pwrdm" },
|
|
.prcm_partition = OMAP4430_PRM_PARTITION,
|
|
.cm_inst = OMAP4430_PRM_EMU_CM_INST,
|
|
.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
|
|
.flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
|
|
CLKDM_MISSING_IDLE_REPORTING),
|
|
};
|
|
|
|
static struct clockdomain l3_dma_44xx_clkdm = {
|
|
.name = "l3_dma_clkdm",
|
|
.pwrdm = { .name = "core_pwrdm" },
|
|
.prcm_partition = OMAP4430_CM2_PARTITION,
|
|
.cm_inst = OMAP4430_CM2_CORE_INST,
|
|
.clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
|
|
.wkdep_srcs = l3_dma_wkup_sleep_deps,
|
|
.sleepdep_srcs = l3_dma_wkup_sleep_deps,
|
|
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
|
};
|
|
|
|
/* As clockdomains are added or removed above, this list must also be changed */
|
|
static struct clockdomain *clockdomains_omap44xx[] __initdata = {
|
|
&l4_cefuse_44xx_clkdm,
|
|
&l4_cfg_44xx_clkdm,
|
|
&tesla_44xx_clkdm,
|
|
&l3_gfx_44xx_clkdm,
|
|
&ivahd_44xx_clkdm,
|
|
&l4_secure_44xx_clkdm,
|
|
&l4_per_44xx_clkdm,
|
|
&abe_44xx_clkdm,
|
|
&l3_instr_44xx_clkdm,
|
|
&l3_init_44xx_clkdm,
|
|
&d2d_44xx_clkdm,
|
|
&mpu0_44xx_clkdm,
|
|
&mpu1_44xx_clkdm,
|
|
&l3_emif_44xx_clkdm,
|
|
&l4_ao_44xx_clkdm,
|
|
&ducati_44xx_clkdm,
|
|
&mpu_44xx_clkdm,
|
|
&l3_2_44xx_clkdm,
|
|
&l3_1_44xx_clkdm,
|
|
&iss_44xx_clkdm,
|
|
&l3_dss_44xx_clkdm,
|
|
&l4_wkup_44xx_clkdm,
|
|
&emu_sys_44xx_clkdm,
|
|
&l3_dma_44xx_clkdm,
|
|
NULL
|
|
};
|
|
|
|
|
|
void __init omap44xx_clockdomains_init(void)
|
|
{
|
|
clkdm_register_platform_funcs(&omap4_clkdm_operations);
|
|
clkdm_register_clkdms(clockdomains_omap44xx);
|
|
clkdm_complete_init();
|
|
}
|