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64dbc3d55d
We can now init system timers using the dmtimer and 32k counter based on only devicetree data and drivers/clocksource timers. Let's configure the clocksource and clockevent, and drop the old unused platform data. As we're just dropping platform data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Since the dmtimer can use both 32k clock and system clock as the source, let's also configure the SoC specific default values. The board specific dts files can reconfigure these with assigned-clocks and assigned-clock-parents as needed. Let's also update the dts file to use #include while at it. Cc: devicetree@vger.kernel.org Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Keerthy <j-keerthy@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Rob Herring <robh@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
403 lines
9.6 KiB
C
403 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
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*
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* Copyright (C) 2009-2011 Nokia Corporation
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* XXX handle crossbar/shared link difference for L3?
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <linux/platform_data/i2c-omap.h>
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#include "omap_hwmod.h"
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#include "l3_2xxx.h"
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#include "l4_2xxx.h"
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#include "omap_hwmod_common_data.h"
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#include "cm-regbits-24xx.h"
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#include "prm-regbits-24xx.h"
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#include "i2c.h"
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#include "mmc.h"
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#include "serial.h"
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#include "wd_timer.h"
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/*
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* OMAP2420 hardware module integration data
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*
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* All of the data in this section should be autogeneratable from the
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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/*
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* IP blocks
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*/
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/* IVA1 (IVA1) */
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static struct omap_hwmod_class iva1_hwmod_class = {
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.name = "iva1",
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};
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static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
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{ .name = "iva", .rst_shift = 8 },
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};
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static struct omap_hwmod omap2420_iva_hwmod = {
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.name = "iva",
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.class = &iva1_hwmod_class,
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.clkdm_name = "iva1_clkdm",
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.rst_lines = omap2420_iva_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
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.main_clk = "iva1_ifck",
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};
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/* DSP */
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static struct omap_hwmod_class dsp_hwmod_class = {
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.name = "dsp",
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};
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static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
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{ .name = "logic", .rst_shift = 0 },
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{ .name = "mmu", .rst_shift = 1 },
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};
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static struct omap_hwmod omap2420_dsp_hwmod = {
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.name = "dsp",
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.class = &dsp_hwmod_class,
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.clkdm_name = "dsp_clkdm",
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.rst_lines = omap2420_dsp_resets,
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.rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
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.main_clk = "dsp_fck",
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};
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/* I2C common */
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static struct omap_hwmod_class_sysconfig i2c_sysc = {
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.rev_offs = 0x00,
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.sysc_offs = 0x20,
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.syss_offs = 0x10,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class i2c_class = {
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.name = "i2c",
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.sysc = &i2c_sysc,
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.reset = &omap_i2c_reset,
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};
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/* I2C1 */
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static struct omap_hwmod omap2420_i2c1_hwmod = {
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.name = "i2c1",
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.main_clk = "i2c1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
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},
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},
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.class = &i2c_class,
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/*
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* From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
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* while a transfer is active seems to cause the I2C block to
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* timeout. Why? Good question."
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*/
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.flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
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};
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/* I2C2 */
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static struct omap_hwmod omap2420_i2c2_hwmod = {
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.name = "i2c2",
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.main_clk = "i2c2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
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},
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},
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.class = &i2c_class,
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.flags = HWMOD_16BIT_REG,
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};
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/* mailbox */
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static struct omap_hwmod omap2420_mailbox_hwmod = {
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.name = "mailbox",
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.class = &omap2xxx_mailbox_hwmod_class,
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.main_clk = "mailboxes_ick",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
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},
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},
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};
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/*
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* 'mcbsp' class
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* multi channel buffered serial port controller
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*/
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static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
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.name = "mcbsp",
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};
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static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
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{ .role = "pad_fck", .clk = "mcbsp_clks" },
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{ .role = "prcm_fck", .clk = "func_96m_ck" },
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};
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/* mcbsp1 */
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static struct omap_hwmod omap2420_mcbsp1_hwmod = {
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.name = "mcbsp1",
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.class = &omap2420_mcbsp_hwmod_class,
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.main_clk = "mcbsp1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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/* mcbsp2 */
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static struct omap_hwmod omap2420_mcbsp2_hwmod = {
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.name = "mcbsp2",
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.class = &omap2420_mcbsp_hwmod_class,
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.main_clk = "mcbsp2_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
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},
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},
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.opt_clks = mcbsp_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
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};
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static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
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.rev_offs = 0x3c,
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.sysc_offs = 0x64,
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.syss_offs = 0x68,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
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.name = "msdi",
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.sysc = &omap2420_msdi_sysc,
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.reset = &omap_msdi_reset,
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};
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/* msdi1 */
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static struct omap_hwmod omap2420_msdi1_hwmod = {
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.name = "msdi1",
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.class = &omap2420_msdi_hwmod_class,
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.main_clk = "mmc_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
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},
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},
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.flags = HWMOD_16BIT_REG,
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};
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/* HDQ1W/1-wire */
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static struct omap_hwmod omap2420_hdq1w_hwmod = {
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.name = "hdq1w",
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.main_clk = "hdq_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
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},
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},
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.class = &omap2_hdq1w_class,
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};
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/*
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* interfaces
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*/
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/* L4 CORE -> I2C1 interface */
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_i2c1_hwmod,
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.clk = "i2c1_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C2 interface */
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_i2c2_hwmod,
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.clk = "i2c2_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* IVA <- L3 interface */
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static struct omap_hwmod_ocp_if omap2420_l3__iva = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2420_iva_hwmod,
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.clk = "core_l3_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* DSP <- L3 interface */
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static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2420_dsp_hwmod,
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.clk = "dsp_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_wd_timer2_hwmod,
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.clk = "mpu_wdt_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio1 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio1_hwmod,
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.clk = "gpios_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio2 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio2_hwmod,
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.clk = "gpios_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio3 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio3_hwmod,
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.clk = "gpios_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_wkup -> gpio4 */
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
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.master = &omap2xxx_l4_wkup_hwmod,
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.slave = &omap2xxx_gpio4_hwmod,
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.clk = "gpios_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> mailbox */
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static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_mailbox_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> mcbsp1 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_mcbsp1_hwmod,
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.clk = "mcbsp1_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> mcbsp2 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_mcbsp2_hwmod,
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.clk = "mcbsp2_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> msdi1 */
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static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_msdi1_hwmod,
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.clk = "mmc_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* l4_core -> hdq1w interface */
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static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
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.master = &omap2xxx_l4_core_hwmod,
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.slave = &omap2420_hdq1w_hwmod,
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.clk = "hdq_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
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};
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static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
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.master = &omap2xxx_l3_main_hwmod,
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.slave = &omap2xxx_gpmc_hwmod,
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.clk = "core_l3_ck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
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&omap2xxx_l3_main__l4_core,
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&omap2xxx_mpu__l3_main,
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&omap2xxx_dss__l3,
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&omap2xxx_l4_core__mcspi1,
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&omap2xxx_l4_core__mcspi2,
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&omap2xxx_l4_core__l4_wkup,
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&omap2_l4_core__uart1,
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&omap2_l4_core__uart2,
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&omap2_l4_core__uart3,
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&omap2420_l4_core__i2c1,
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&omap2420_l4_core__i2c2,
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&omap2420_l3__iva,
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&omap2420_l3__dsp,
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&omap2xxx_l4_core__timer3,
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&omap2xxx_l4_core__timer4,
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&omap2xxx_l4_core__timer5,
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&omap2xxx_l4_core__timer6,
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&omap2xxx_l4_core__timer7,
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&omap2xxx_l4_core__timer8,
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&omap2xxx_l4_core__timer9,
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&omap2xxx_l4_core__timer10,
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&omap2xxx_l4_core__timer11,
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&omap2xxx_l4_core__timer12,
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&omap2420_l4_wkup__wd_timer2,
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&omap2xxx_l4_core__dss,
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&omap2xxx_l4_core__dss_dispc,
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&omap2xxx_l4_core__dss_rfbi,
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&omap2xxx_l4_core__dss_venc,
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&omap2420_l4_wkup__gpio1,
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&omap2420_l4_wkup__gpio2,
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&omap2420_l4_wkup__gpio3,
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&omap2420_l4_wkup__gpio4,
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&omap2420_l4_core__mailbox,
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&omap2420_l4_core__mcbsp1,
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&omap2420_l4_core__mcbsp2,
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&omap2420_l4_core__msdi1,
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&omap2xxx_l4_core__rng,
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&omap2xxx_l4_core__sham,
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&omap2xxx_l4_core__aes,
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&omap2420_l4_core__hdq1w,
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&omap2420_l3__gpmc,
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NULL,
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};
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int __init omap2420_hwmod_init(void)
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{
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omap_hwmod_init();
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return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
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}
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