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7f9942c61f
Building with the clang integrated assembler produces a couple of
errors for the s3c24xx fiq support:
arch/arm/mach-s3c/irq-s3c24xx-fiq.S:52:2: error: instruction 'subne' can not set flags, but 's' suffix specified
subnes pc, lr, #4 @@ return, still have work to do
arch/arm/mach-s3c/irq-s3c24xx-fiq.S:64:1: error: invalid symbol redefinition
s3c24xx_spi_fiq_txrx:
There are apparently two problems: one with extraneous or duplicate
labels, and one with old-style opcode mnemonics. Stefan Agner has
previously fixed other problems like this, but missed this particular
file.
Fixes: bec0806cfe ("spi_s3c24xx: add FIQ pseudo-DMA support")
Cc: Stefan Agner <stefan@agner.ch>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nathan Chancellor <nathan@kernel.org>
Link: https://lore.kernel.org/r/20210204162416.3030114-1-arnd@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
112 lines
2.7 KiB
ArmAsm
112 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/* linux/drivers/spi/spi_s3c24xx_fiq.S
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*
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* Copyright 2009 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX SPI - FIQ pseudo-DMA transfer code
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "map.h"
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#include "regs-irq.h"
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#include <linux/spi/s3c24xx-fiq.h>
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#define S3C2410_SPTDAT (0x10)
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#define S3C2410_SPRDAT (0x14)
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.text
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@ entry to these routines is as follows, with the register names
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@ defined in fiq.h so that they can be shared with the C files which
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@ setup the calling registers.
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@
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@ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND
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@ fiq_rtmp Temporary register to hold tx/rx data
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@ fiq_rspi The base of the SPI register block
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@ fiq_rtx The tx buffer pointer
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@ fiq_rrx The rx buffer pointer
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@ fiq_rcount The number of bytes to move
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@ each entry starts with a word entry of how long it is
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@ and an offset to the irq acknowledgment word
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ENTRY(s3c24xx_spi_fiq_rx)
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.word fiq_rx_end - fiq_rx_start
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.word fiq_rx_irq_ack - fiq_rx_start
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fiq_rx_start:
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ldr fiq_rtmp, fiq_rx_irq_ack
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str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
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ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
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strb fiq_rtmp, [ fiq_rrx ], #1
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mov fiq_rtmp, #0xff
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strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
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subs fiq_rcount, fiq_rcount, #1
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subsne pc, lr, #4 @@ return, still have work to do
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@@ set IRQ controller so that next op will trigger IRQ
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mov fiq_rtmp, #0
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str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
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subs pc, lr, #4
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fiq_rx_irq_ack:
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.word 0
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fiq_rx_end:
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ENTRY(s3c24xx_spi_fiq_txrx)
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.word fiq_txrx_end - fiq_txrx_start
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.word fiq_txrx_irq_ack - fiq_txrx_start
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fiq_txrx_start:
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ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
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strb fiq_rtmp, [ fiq_rrx ], #1
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ldr fiq_rtmp, fiq_txrx_irq_ack
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str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
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ldrb fiq_rtmp, [ fiq_rtx ], #1
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strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
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subs fiq_rcount, fiq_rcount, #1
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subsne pc, lr, #4 @@ return, still have work to do
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mov fiq_rtmp, #0
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str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
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subs pc, lr, #4
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fiq_txrx_irq_ack:
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.word 0
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fiq_txrx_end:
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ENTRY(s3c24xx_spi_fiq_tx)
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.word fiq_tx_end - fiq_tx_start
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.word fiq_tx_irq_ack - fiq_tx_start
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fiq_tx_start:
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ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ]
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ldr fiq_rtmp, fiq_tx_irq_ack
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str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ]
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ldrb fiq_rtmp, [ fiq_rtx ], #1
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strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ]
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subs fiq_rcount, fiq_rcount, #1
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subsne pc, lr, #4 @@ return, still have work to do
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mov fiq_rtmp, #0
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str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ]
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subs pc, lr, #4
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fiq_tx_irq_ack:
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.word 0
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fiq_tx_end:
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.end
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