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c78a41fc04
As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
213 lines
4.8 KiB
C
213 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2003-2004 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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//
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// https://www.handhelds.org/projects/rx3715.html
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/memblock.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/tty.h>
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#include <linux/console.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand-ecc-sw-hamming.h>
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#include <linux/mtd/partitions.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#include <linux/platform_data/fb-s3c2410.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include "regs-gpio.h"
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#include "gpio-samsung.h"
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#include "gpio-cfg.h"
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#include "cpu.h"
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#include "devs.h"
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#include "pm.h"
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#include "s3c24xx.h"
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#include "h1940.h"
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static struct map_desc rx3715_iodesc[] __initdata = {
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/* dump ISA space somewhere unused */
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{
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS3),
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.length = SZ_1M,
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.type = MT_DEVICE,
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},
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};
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static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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.clk_sel = S3C2410_UCON_CLKSEL3,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x00,
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.clk_sel = S3C2410_UCON_CLKSEL3,
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},
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/* IR port */
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[2] = {
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.hwport = 2,
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.uart_flags = UPF_CONS_FLOW,
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.ucon = 0x3c5,
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.ulcon = 0x43,
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.ufcon = 0x51,
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.clk_sel = S3C2410_UCON_CLKSEL3,
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}
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};
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/* framebuffer lcd controller information */
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static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
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.lcdcon5 = S3C2410_LCDCON5_INVVLINE |
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S3C2410_LCDCON5_FRM565 |
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S3C2410_LCDCON5_HWSWP,
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.type = S3C2410_LCDCON1_TFT,
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.width = 240,
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.height = 320,
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.pixclock = 260000,
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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.left_margin = 36,
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.right_margin = 36,
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.hsync_len = 8,
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.upper_margin = 6,
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.lower_margin = 7,
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.vsync_len = 3,
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};
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static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
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.displays = &rx3715_lcdcfg,
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.num_displays = 1,
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.default_display = 0,
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.lpcsel = 0xf82,
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.gpccon = 0xaa955699,
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.gpccon_mask = 0xffc003cc,
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.gpccon_reg = S3C2410_GPCCON,
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.gpcup = 0x0000ffff,
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.gpcup_mask = 0xffffffff,
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.gpcup_reg = S3C2410_GPCUP,
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.gpdcon = 0xaa95aaa1,
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.gpdcon_mask = 0xffc0fff0,
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.gpdcon_reg = S3C2410_GPDCON,
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.gpdup = 0x0000faff,
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.gpdup_mask = 0xffffffff,
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.gpdup_reg = S3C2410_GPDUP,
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};
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static struct mtd_partition __initdata rx3715_nand_part[] = {
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[0] = {
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.name = "Whole Flash",
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.offset = 0,
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.size = MTDPART_SIZ_FULL,
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.mask_flags = MTD_WRITEABLE,
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}
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};
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static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
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[0] = {
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.name = "Internal",
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.nr_chips = 1,
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.nr_partitions = ARRAY_SIZE(rx3715_nand_part),
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.partitions = rx3715_nand_part,
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},
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};
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static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
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.tacls = 25,
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.twrph0 = 50,
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.twrph1 = 15,
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.nr_sets = ARRAY_SIZE(rx3715_nand_sets),
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.sets = rx3715_nand_sets,
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.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
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};
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static struct platform_device *rx3715_devices[] __initdata = {
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&s3c_device_ohci,
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&s3c_device_lcd,
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&s3c_device_wdt,
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&s3c_device_i2c0,
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&s3c_device_iis,
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&s3c_device_nand,
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};
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static void __init rx3715_map_io(void)
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{
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s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
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s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
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s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
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}
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static void __init rx3715_init_time(void)
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{
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s3c2440_init_clocks(16934000);
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s3c24xx_timer_init();
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}
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/* H1940 and RX3715 need to reserve this for suspend */
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static void __init rx3715_reserve(void)
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{
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memblock_reserve(0x30003000, 0x1000);
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memblock_reserve(0x30081000, 0x1000);
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}
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static void __init rx3715_init_machine(void)
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{
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#ifdef CONFIG_PM_H1940
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memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
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#endif
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s3c_pm_init();
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s3c_nand_set_platdata(&rx3715_nand_info);
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s3c24xx_fb_set_platdata(&rx3715_fb_info);
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/* Configure the I2S pins (GPE0...GPE4) in correct mode */
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s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
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S3C_GPIO_PULL_NONE);
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platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
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}
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MACHINE_START(RX3715, "IPAQ-RX3715")
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/* Maintainer: Ben Dooks <ben-linux@fluff.org> */
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.atag_offset = 0x100,
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.nr_irqs = NR_IRQS_S3C2440,
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.map_io = rx3715_map_io,
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.reserve = rx3715_reserve,
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.init_irq = s3c2440_init_irq,
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.init_machine = rx3715_init_machine,
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.init_time = rx3715_init_time,
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MACHINE_END
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