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c78a41fc04
As a final bit of preparation for converting to ARCH_MULTIPLATFORM, change the interrupt handling for s3c24xx to use sparse IRQs. Since the number of possible interrupts is already fixed and relatively small per chip, just make it use all legacy interrupts preallocated using the .nr_irqs field in the machine descriptor, rather than actually allocating domains on the fly. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
166 lines
3.5 KiB
C
166 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// (C) 2006 Thomas Gleixner <tglx@linutronix.de>
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//
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// Derived from mach-smdk2413.c - (C) 2006 Simtec Electronics
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/nand-ecc-sw-hamming.h>
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#include <linux/mtd/partitions.h>
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#include <linux/memblock.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include "regs-gpio.h"
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#include "gpio-samsung.h"
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#include "gpio-cfg.h"
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#include <linux/platform_data/fb-s3c2410.h>
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#include <linux/platform_data/i2c-s3c2410.h>
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#include <linux/platform_data/mtd-nand-s3c2410.h>
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#include "devs.h"
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#include "cpu.h"
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#include "s3c24xx.h"
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static struct map_desc vstms_iodesc[] __initdata = {
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};
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static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = 0x3c5,
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.ulcon = 0x03,
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.ufcon = 0x51,
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}
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};
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static struct mtd_partition __initdata vstms_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = 0x7C000,
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.offset = 0,
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},
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[1] = {
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.name = "UBoot Config",
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.offset = 0x7C000,
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.size = 0x4000,
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},
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[2] = {
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.name = "Kernel",
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.offset = 0x80000,
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.size = 0x200000,
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},
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[3] = {
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.name = "RFS",
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.offset = 0x280000,
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.size = 0x3d80000,
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},
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};
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static struct s3c2410_nand_set __initdata vstms_nand_sets[] = {
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[0] = {
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.name = "NAND",
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.nr_chips = 1,
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.nr_partitions = ARRAY_SIZE(vstms_nand_part),
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.partitions = vstms_nand_part,
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},
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};
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/* choose a set of timings which should suit most 512Mbit
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* chips and beyond.
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*/
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static struct s3c2410_platform_nand __initdata vstms_nand_info = {
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.tacls = 20,
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.twrph0 = 60,
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.twrph1 = 20,
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.nr_sets = ARRAY_SIZE(vstms_nand_sets),
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.sets = vstms_nand_sets,
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.engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
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};
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static struct platform_device *vstms_devices[] __initdata = {
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&s3c_device_ohci,
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&s3c_device_wdt,
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&s3c_device_i2c0,
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&s3c_device_iis,
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&s3c_device_rtc,
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&s3c_device_nand,
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&s3c2412_device_dma,
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};
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static void __init vstms_fixup(struct tag *tags, char **cmdline)
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{
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if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
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memblock_add(0x30000000, SZ_64M);
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}
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}
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static void __init vstms_map_io(void)
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{
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s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
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s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
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s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
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}
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static void __init vstms_init_time(void)
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{
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s3c2412_init_clocks(12000000);
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s3c24xx_timer_init();
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}
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static void __init vstms_init(void)
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{
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s3c_i2c0_set_platdata(NULL);
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s3c_nand_set_platdata(&vstms_nand_info);
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/* Configure the I2S pins (GPE0...GPE4) in correct mode */
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s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2),
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S3C_GPIO_PULL_NONE);
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platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
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}
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MACHINE_START(VSTMS, "VSTMS")
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.atag_offset = 0x100,
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.nr_irqs = NR_IRQS_S3C2412,
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.fixup = vstms_fixup,
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.init_irq = s3c2412_init_irq,
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.init_machine = vstms_init,
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.map_io = vstms_map_io,
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.init_time = vstms_init_time,
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MACHINE_END
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