mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
ecf0aa5317
This series has been 12 years in the making, it mostly finishes the work that was started with the founding of Linaro to clean up platform support in the kernel. The largest change here is a cleanup of the omap1 platform, which is the final ARM machine type to get converted to the common-clk subsystem. All the omap1 specific drivers are now made independent of the mach/*.h headers to allow the platform to be part of a generic ARMv4/v5 multiplatform kernel. The last bit that enables this support is still missing here while we wait for some last dependencies to make it into the mainline kernel through other subsystems. The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost at the point of allowing multiplatform kernels, this work gets completed here along with a few additional cleanup. At the same time, the s3c24xx and s3c64xx are now deprecated and expected to get removed in the future. The PXA and OMAP1 bits are in a separate branch because of dependencies. Once both branches are merged, only the three Intel StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels, and there are no plans to include these. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmKOP3sACgkQmmx57+YA GNk+DhAAmrPNuS8JDlCRPa76Nd9PC9aitnnEGYytQ6bgwexKd3qdvP7gdUtr7jlV 8k4KiGnnZZjEGd4i5cAVhSCyBbCt4oPKhato62KneEsO19xLsVmmTpQg1LPK75do mHYKpc+6932Lp6WrtI1F75id0phx684tpZp9P4ggXwMwgYkagq9rcO+mGUNZWDc8 D9SdAmoObtSCoBCYYbq2VhAPA79mSKKVpLGehzd+Gq5cuf/jJQD0u1E00izkdyZc r/5acQ7PHQlVXqSONYgCpkvDTqmjg9cvVCKeKLpFspV3f6vBVRgV60UGfwhpdPHY N119KUJtPf81xnLSxsqBFA34LMSerrH72YM5cYupKiiYcTDr+Yw6zrtNR6ktkt/B F1Tc/QV+A9CGergxljy39G1smEuwKtNiVA//NSlUORCHxgwa5XUB0mQIzNcWARa4 oMDLhBF7ES211CB7Yto2FR6gBQbh2A9HSpjOh6kxdHrRb4FCgoXjPhzBoMxPoSFu XIzJpMb18K4bI+hKRYddEOK5V0kHt9mzT7ViGT/2+n13IHKIGmKrZxwDH7mohAW9 4GF77gGbQsE9szajkx5EG1t+PWextQeeMyYW05bXO/mbDwA0n7EdjGpBeedvTZw3 6gUWVahfYp9hZWPdxJ4fbGnlbSovCq0y4tj5fbZHPh6AOAtmvWY= =CTtN -----END PGP SIGNATURE----- Merge tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARMv4T/v5 multiplatform support from Arnd Bergmann: "This series has been 12 years in the making, it mostly finishes the work that was started with the founding of Linaro to clean up platform support in the kernel. The largest change here is a cleanup of the omap1 platform, which is the final ARM machine type to get converted to the common-clk subsystem. All the omap1 specific drivers are now made independent of the mach/*.h headers to allow the platform to be part of a generic ARMv4/v5 multiplatform kernel. The last bit that enables this support is still missing here while we wait for some last dependencies to make it into the mainline kernel through other subsystems. The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost at the point of allowing multiplatform kernels, this work gets completed here along with a few additional cleanup. At the same time, the s3c24xx and s3c64xx are now deprecated and expected to get removed in the future. The PXA and OMAP1 bits are in a separate branch because of dependencies. Once both branches are merged, only the three Intel StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels, and there are no plans to include these" * tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits) ARM: ixp4xx: Consolidate Kconfig fixing issue ARM: versatile: Add missing of_node_put in dcscb_init ARM: config: Refresh IXP4xx config after multiplatform ARM: omap1: add back omap_set_dma_priority() stub ARM: omap: fix missing declaration warnings ARM: omap: fix address space warnings from sparse ARM: spear: remove include/mach/ subdirectory ARM: davinci: remove include/mach/ subdirectory ARM: omap2: remove include/mach/ subdirectory integrator: remove empty ap_init_early() ARM: s3c: fix include path MAINTAINERS: omap1: Add Janusz as an additional maintainer ARM: omap1: htc_herald: fix typos in comments ARM: OMAP1: fix typos in comments ARM: OMAP1: clock: Remove noop code ARM: OMAP1: clock: Remove unused code ARM: OMAP1: clock: Fix UART rate reporting algorithm ARM: OMAP1: clock: Fix early UART rate issues ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF ARM: omap1: fix build with no SoC selected ...
687 lines
22 KiB
C
687 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (c) 2004-2005 Simtec Electronics
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// http://www.simtec.co.uk/products/SWLINUX/
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// Ben Dooks <ben@simtec.co.uk>
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//
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// Common code for S3C24XX machines
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <clocksource/samsung_pwm.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_data/clk-s3c2410.h>
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#include <linux/platform_data/dma-s3c24xx.h>
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#include <linux/dmaengine.h>
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#include <linux/clk/samsung.h>
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#include "hardware-s3c24xx.h"
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#include "map.h"
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#include "regs-clock.h"
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#include <asm/irq.h>
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#include <asm/cacheflush.h>
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#include <asm/system_info.h>
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#include <asm/system_misc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "regs-gpio.h"
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#include "dma-s3c24xx.h"
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#include "cpu.h"
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#include "devs.h"
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#include "pwm-core.h"
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#include "s3c24xx.h"
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/* table of supported CPUs */
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static const char name_s3c2410[] = "S3C2410";
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static const char name_s3c2412[] = "S3C2412";
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static const char name_s3c2416[] = "S3C2416/S3C2450";
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static const char name_s3c2440[] = "S3C2440";
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static const char name_s3c2442[] = "S3C2442";
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static const char name_s3c2442b[] = "S3C2442B";
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static const char name_s3c2443[] = "S3C2443";
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static const char name_s3c2410a[] = "S3C2410A";
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static const char name_s3c2440a[] = "S3C2440A";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = 0x32410000,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410_init,
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.name = name_s3c2410
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},
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{
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.idcode = 0x32410002,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410a_init,
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.name = name_s3c2410a
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},
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{
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.idcode = 0x32440000,
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.idmask = 0xffffffff,
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.map_io = s3c2440_map_io,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440
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},
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{
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.idcode = 0x32440001,
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.idmask = 0xffffffff,
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.map_io = s3c2440_map_io,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440a
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},
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{
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.idcode = 0x32440aaa,
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.idmask = 0xffffffff,
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.map_io = s3c2442_map_io,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2442_init,
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.name = name_s3c2442
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},
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{
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.idcode = 0x32440aab,
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.idmask = 0xffffffff,
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.map_io = s3c2442_map_io,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2442_init,
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.name = name_s3c2442b
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},
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{
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.idcode = 0x32412001,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{ /* a newer version of the s3c2412 */
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.idcode = 0x32412003,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{ /* a strange version of the s3c2416 */
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.idcode = 0x32450003,
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.idmask = 0xffffffff,
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.map_io = s3c2416_map_io,
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.init_uarts = s3c2416_init_uarts,
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.init = s3c2416_init,
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.name = name_s3c2416,
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},
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{
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.idcode = 0x32443001,
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.idmask = 0xffffffff,
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.map_io = s3c2443_map_io,
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.init_uarts = s3c2443_init_uarts,
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.init = s3c2443_init,
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.name = name_s3c2443,
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},
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};
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/* minimal IO mapping */
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static struct map_desc s3c_iodesc[] __initdata __maybe_unused = {
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IODESC_ENT(GPIO),
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IODESC_ENT(IRQ),
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IODESC_ENT(MEMCTRL),
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IODESC_ENT(UART)
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};
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/* read cpu identification code */
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static unsigned long s3c24xx_read_idcode_v5(void)
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{
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#if defined(CONFIG_CPU_S3C2416)
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/* s3c2416 is v5, with S3C24XX_GSTATUS1 instead of S3C2412_GSTATUS1 */
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u32 gs = __raw_readl(S3C24XX_GSTATUS1);
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/* test for s3c2416 or similar device */
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if ((gs >> 16) == 0x3245)
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return gs;
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#endif
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#if defined(CONFIG_CPU_S3C2412)
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return __raw_readl(S3C2412_GSTATUS1);
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#else
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return 1UL; /* don't look like an 2400 */
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#endif
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}
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static unsigned long s3c24xx_read_idcode_v4(void)
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{
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return __raw_readl(S3C2410_GSTATUS1);
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}
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static void s3c24xx_default_idle(void)
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{
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unsigned long tmp = 0;
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int i;
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/* idle the system by using the idle mode which will wait for an
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* interrupt to happen before restarting the system.
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*/
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/* Warning: going into idle state upsets jtag scanning */
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__raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
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S3C2410_CLKCON);
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/* the samsung port seems to do a loop and then unset idle.. */
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for (i = 0; i < 50; i++)
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tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
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/* this bit is not cleared on re-start... */
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__raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
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S3C2410_CLKCON);
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}
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static struct samsung_pwm_variant s3c24xx_pwm_variant = {
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.bits = 16,
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.div_base = 1,
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.has_tint_cstat = false,
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.tclk_mask = (1 << 4),
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};
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void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
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{
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arm_pm_idle = s3c24xx_default_idle;
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/* initialise the io descriptors we need for initialisation */
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iotable_init(mach_desc, size);
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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if (cpu_architecture() >= CPU_ARCH_ARMv5) {
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samsung_cpu_id = s3c24xx_read_idcode_v5();
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} else {
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samsung_cpu_id = s3c24xx_read_idcode_v4();
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}
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
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samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
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}
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void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source)
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{
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s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
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s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
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}
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void __init s3c24xx_timer_init(void)
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{
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unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
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IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
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};
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samsung_pwm_clocksource_init(S3C_VA_TIMER,
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timer_irqs, &s3c24xx_pwm_variant);
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}
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/* Serial port registrations */
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#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
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#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
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#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
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#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
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static struct resource s3c2410_uart0_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
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IRQ_S3CUART_ERR0 - IRQ_S3CUART_RX0 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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static struct resource s3c2410_uart1_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_PA_UART1, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX1, \
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IRQ_S3CUART_ERR1 - IRQ_S3CUART_RX1 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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static struct resource s3c2410_uart2_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2410_PA_UART2, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX2, \
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IRQ_S3CUART_ERR2 - IRQ_S3CUART_RX2 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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static struct resource s3c2410_uart3_resource[] = {
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[0] = DEFINE_RES_MEM(S3C2443_PA_UART3, SZ_16K),
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[1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX3, \
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IRQ_S3CUART_ERR3 - IRQ_S3CUART_RX3 + 1, \
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NULL, IORESOURCE_IRQ)
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};
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struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
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[0] = {
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.resources = s3c2410_uart0_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
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},
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[1] = {
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.resources = s3c2410_uart1_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
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},
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[2] = {
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.resources = s3c2410_uart2_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
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},
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[3] = {
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.resources = s3c2410_uart3_resource,
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.nr_resources = ARRAY_SIZE(s3c2410_uart3_resource),
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},
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};
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#define s3c24xx_device_dma_mask (*((u64[]) { DMA_BIT_MASK(32) }))
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#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
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defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
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static struct resource s3c2410_dma_resource[] = {
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[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
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[1] = DEFINE_RES_IRQ(IRQ_DMA0),
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[2] = DEFINE_RES_IRQ(IRQ_DMA1),
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[3] = DEFINE_RES_IRQ(IRQ_DMA2),
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[4] = DEFINE_RES_IRQ(IRQ_DMA3),
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};
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#endif
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#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442)
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static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = {
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[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
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[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
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[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
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S3C24XX_DMA_CHANREQ(2, 2) |
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S3C24XX_DMA_CHANREQ(1, 3),
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},
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[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
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[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
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[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
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[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
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[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
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[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
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S3C24XX_DMA_CHANREQ(3, 2) |
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S3C24XX_DMA_CHANREQ(3, 3),
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},
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[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
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S3C24XX_DMA_CHANREQ(1, 2),
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},
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[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), },
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[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
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[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
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[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
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[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
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};
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static const struct dma_slave_map s3c2410_dma_slave_map[] = {
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{ "s3c2410-sdi", "rx-tx", (void *)DMACH_SDI },
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{ "s3c2410-spi.0", "rx", (void *)DMACH_SPI0_RX },
|
|
{ "s3c2410-spi.0", "tx", (void *)DMACH_SPI0_TX },
|
|
{ "s3c2410-spi.1", "rx", (void *)DMACH_SPI1_RX },
|
|
{ "s3c2410-spi.1", "tx", (void *)DMACH_SPI1_TX },
|
|
/*
|
|
* The DMA request source[1] (DMACH_UARTx_SRC2) are
|
|
* not used in the UART driver.
|
|
*/
|
|
{ "s3c2410-uart.0", "rx", (void *)DMACH_UART0 },
|
|
{ "s3c2410-uart.0", "tx", (void *)DMACH_UART0 },
|
|
{ "s3c2410-uart.1", "rx", (void *)DMACH_UART1 },
|
|
{ "s3c2410-uart.1", "tx", (void *)DMACH_UART1 },
|
|
{ "s3c2410-uart.2", "rx", (void *)DMACH_UART2 },
|
|
{ "s3c2410-uart.2", "tx", (void *)DMACH_UART2 },
|
|
{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
|
|
{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
|
|
{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
|
|
{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
|
|
{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
|
|
{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
|
|
{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
|
|
{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
|
|
{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
|
|
{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
|
|
};
|
|
|
|
static struct s3c24xx_dma_platdata s3c2410_dma_platdata = {
|
|
.num_phy_channels = 4,
|
|
.channels = s3c2410_dma_channels,
|
|
.num_channels = DMACH_MAX,
|
|
.slave_map = s3c2410_dma_slave_map,
|
|
.slavecnt = ARRAY_SIZE(s3c2410_dma_slave_map),
|
|
};
|
|
|
|
struct platform_device s3c2410_device_dma = {
|
|
.name = "s3c2410-dma",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
|
|
.resource = s3c2410_dma_resource,
|
|
.dev = {
|
|
.dma_mask = &s3c24xx_device_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &s3c2410_dma_platdata,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2412
|
|
static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = {
|
|
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
|
|
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
|
|
[DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
|
|
[DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
|
|
[DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
|
|
[DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
|
|
[DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
|
|
[DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
|
|
[DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
|
|
[DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
|
|
[DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
|
|
[DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
|
|
[DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
|
|
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
|
|
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
|
|
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
|
|
[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 },
|
|
[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 },
|
|
[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 },
|
|
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 },
|
|
};
|
|
|
|
static const struct dma_slave_map s3c2412_dma_slave_map[] = {
|
|
{ "s3c2412-sdi", "rx-tx", (void *)DMACH_SDI },
|
|
{ "s3c2412-spi.0", "rx", (void *)DMACH_SPI0_RX },
|
|
{ "s3c2412-spi.0", "tx", (void *)DMACH_SPI0_TX },
|
|
{ "s3c2412-spi.1", "rx", (void *)DMACH_SPI1_RX },
|
|
{ "s3c2412-spi.1", "tx", (void *)DMACH_SPI1_TX },
|
|
{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
|
|
{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
|
|
{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
|
|
{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
|
|
{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
|
|
{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
|
|
{ "s3c2412-iis", "rx", (void *)DMACH_I2S_IN },
|
|
{ "s3c2412-iis", "tx", (void *)DMACH_I2S_OUT },
|
|
{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
|
|
{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
|
|
{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
|
|
{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
|
|
{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
|
|
{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
|
|
{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
|
|
{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
|
|
};
|
|
|
|
static struct s3c24xx_dma_platdata s3c2412_dma_platdata = {
|
|
.num_phy_channels = 4,
|
|
.channels = s3c2412_dma_channels,
|
|
.num_channels = DMACH_MAX,
|
|
.slave_map = s3c2412_dma_slave_map,
|
|
.slavecnt = ARRAY_SIZE(s3c2412_dma_slave_map),
|
|
};
|
|
|
|
struct platform_device s3c2412_device_dma = {
|
|
.name = "s3c2412-dma",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
|
|
.resource = s3c2410_dma_resource,
|
|
.dev = {
|
|
.dma_mask = &s3c24xx_device_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &s3c2412_dma_platdata,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_S3C2440)
|
|
static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = {
|
|
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), },
|
|
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), },
|
|
[DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) |
|
|
S3C24XX_DMA_CHANREQ(6, 1) |
|
|
S3C24XX_DMA_CHANREQ(2, 2) |
|
|
S3C24XX_DMA_CHANREQ(1, 3),
|
|
},
|
|
[DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), },
|
|
[DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), },
|
|
[DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), },
|
|
[DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), },
|
|
[DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), },
|
|
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) |
|
|
S3C24XX_DMA_CHANREQ(3, 2) |
|
|
S3C24XX_DMA_CHANREQ(3, 3),
|
|
},
|
|
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) |
|
|
S3C24XX_DMA_CHANREQ(1, 2),
|
|
},
|
|
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) |
|
|
S3C24XX_DMA_CHANREQ(0, 2),
|
|
},
|
|
[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) |
|
|
S3C24XX_DMA_CHANREQ(5, 2),
|
|
},
|
|
[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) |
|
|
S3C24XX_DMA_CHANREQ(6, 3),
|
|
},
|
|
[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) |
|
|
S3C24XX_DMA_CHANREQ(5, 3),
|
|
},
|
|
[DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), },
|
|
[DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), },
|
|
[DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), },
|
|
[DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), },
|
|
};
|
|
|
|
static const struct dma_slave_map s3c2440_dma_slave_map[] = {
|
|
/* TODO: DMACH_XD0 */
|
|
/* TODO: DMACH_XD1 */
|
|
{ "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
|
|
{ "s3c2410-spi.0", "rx", (void *)DMACH_SPI0 },
|
|
{ "s3c2410-spi.0", "tx", (void *)DMACH_SPI0 },
|
|
{ "s3c2410-spi.1", "rx", (void *)DMACH_SPI1 },
|
|
{ "s3c2410-spi.1", "tx", (void *)DMACH_SPI1 },
|
|
{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
|
|
{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
|
|
{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
|
|
{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
|
|
{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
|
|
{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
|
|
{ "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
|
|
{ "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
|
|
/* TODO: DMACH_TIMER */
|
|
{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
|
|
{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
|
|
{ "samsung-ac97", "rx", (void *)DMACH_PCM_IN },
|
|
{ "samsung-ac97", "tx", (void *)DMACH_PCM_OUT },
|
|
{ "samsung-ac97", "rx", (void *)DMACH_MIC_IN },
|
|
{ "s3c-hsudc", "rx0", (void *)DMACH_USB_EP1 },
|
|
{ "s3c-hsudc", "rx1", (void *)DMACH_USB_EP2 },
|
|
{ "s3c-hsudc", "rx2", (void *)DMACH_USB_EP3 },
|
|
{ "s3c-hsudc", "rx3", (void *)DMACH_USB_EP4 },
|
|
{ "s3c-hsudc", "tx0", (void *)DMACH_USB_EP1 },
|
|
{ "s3c-hsudc", "tx1", (void *)DMACH_USB_EP2 },
|
|
{ "s3c-hsudc", "tx2", (void *)DMACH_USB_EP3 },
|
|
{ "s3c-hsudc", "tx3", (void *)DMACH_USB_EP4 }
|
|
};
|
|
|
|
static struct s3c24xx_dma_platdata s3c2440_dma_platdata = {
|
|
.num_phy_channels = 4,
|
|
.channels = s3c2440_dma_channels,
|
|
.num_channels = DMACH_MAX,
|
|
.slave_map = s3c2440_dma_slave_map,
|
|
.slavecnt = ARRAY_SIZE(s3c2440_dma_slave_map),
|
|
};
|
|
|
|
struct platform_device s3c2440_device_dma = {
|
|
.name = "s3c2410-dma",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(s3c2410_dma_resource),
|
|
.resource = s3c2410_dma_resource,
|
|
.dev = {
|
|
.dma_mask = &s3c24xx_device_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &s3c2440_dma_platdata,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
|
|
static struct resource s3c2443_dma_resource[] = {
|
|
[0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA),
|
|
[1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0),
|
|
[2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1),
|
|
[3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2),
|
|
[4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3),
|
|
[5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4),
|
|
[6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5),
|
|
};
|
|
|
|
static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = {
|
|
[DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 },
|
|
[DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 },
|
|
[DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 },
|
|
[DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 },
|
|
[DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 },
|
|
[DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 },
|
|
[DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 },
|
|
[DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 },
|
|
[DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 },
|
|
[DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 },
|
|
[DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 },
|
|
[DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 },
|
|
[DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 },
|
|
[DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 },
|
|
[DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 },
|
|
[DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 },
|
|
[DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 },
|
|
[DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 },
|
|
[DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 },
|
|
[DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 },
|
|
[DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 },
|
|
};
|
|
|
|
static const struct dma_slave_map s3c2443_dma_slave_map[] = {
|
|
{ "s3c2440-sdi", "rx-tx", (void *)DMACH_SDI },
|
|
{ "s3c2443-spi.0", "rx", (void *)DMACH_SPI0_RX },
|
|
{ "s3c2443-spi.0", "tx", (void *)DMACH_SPI0_TX },
|
|
{ "s3c2443-spi.1", "rx", (void *)DMACH_SPI1_RX },
|
|
{ "s3c2443-spi.1", "tx", (void *)DMACH_SPI1_TX },
|
|
{ "s3c2440-uart.0", "rx", (void *)DMACH_UART0 },
|
|
{ "s3c2440-uart.0", "tx", (void *)DMACH_UART0 },
|
|
{ "s3c2440-uart.1", "rx", (void *)DMACH_UART1 },
|
|
{ "s3c2440-uart.1", "tx", (void *)DMACH_UART1 },
|
|
{ "s3c2440-uart.2", "rx", (void *)DMACH_UART2 },
|
|
{ "s3c2440-uart.2", "tx", (void *)DMACH_UART2 },
|
|
{ "s3c2440-uart.3", "rx", (void *)DMACH_UART3 },
|
|
{ "s3c2440-uart.3", "tx", (void *)DMACH_UART3 },
|
|
{ "s3c24xx-iis", "rx", (void *)DMACH_I2S_IN },
|
|
{ "s3c24xx-iis", "tx", (void *)DMACH_I2S_OUT },
|
|
};
|
|
|
|
static struct s3c24xx_dma_platdata s3c2443_dma_platdata = {
|
|
.num_phy_channels = 6,
|
|
.channels = s3c2443_dma_channels,
|
|
.num_channels = DMACH_MAX,
|
|
.slave_map = s3c2443_dma_slave_map,
|
|
.slavecnt = ARRAY_SIZE(s3c2443_dma_slave_map),
|
|
};
|
|
|
|
struct platform_device s3c2443_device_dma = {
|
|
.name = "s3c2443-dma",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(s3c2443_dma_resource),
|
|
.resource = s3c2443_dma_resource,
|
|
.dev = {
|
|
.dma_mask = &s3c24xx_device_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &s3c2443_dma_platdata,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
|
|
void __init s3c2410_init_clocks(int xtal)
|
|
{
|
|
s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2412
|
|
void __init s3c2412_init_clocks(int xtal)
|
|
{
|
|
s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2416
|
|
void __init s3c2416_init_clocks(int xtal)
|
|
{
|
|
s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
|
|
void __init s3c2440_init_clocks(int xtal)
|
|
{
|
|
s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
|
|
void __init s3c2442_init_clocks(int xtal)
|
|
{
|
|
s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPU_S3C2443
|
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void __init s3c2443_init_clocks(int xtal)
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{
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s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
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}
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#endif
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#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
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defined(CONFIG_CPU_S3C2442)
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static struct resource s3c2410_dclk_resource[] = {
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[0] = DEFINE_RES_MEM(0x56000084, 0x4),
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};
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static struct s3c2410_clk_platform_data s3c_clk_platform_data = {
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.modify_misccr = s3c2410_modify_misccr,
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};
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struct platform_device s3c2410_device_dclk = {
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.name = "s3c2410-dclk",
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.id = 0,
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.num_resources = ARRAY_SIZE(s3c2410_dclk_resource),
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.resource = s3c2410_dclk_resource,
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.dev = {
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.platform_data = &s3c_clk_platform_data,
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},
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};
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#endif
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#ifndef CONFIG_COMPILE_TEST
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#pragma message "The platform is deprecated and scheduled for removal. " \
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"Please reach to the maintainers of the platform " \
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"and linux-samsung-soc@vger.kernel.org if you still use it." \
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"Without such feedback, the platform will be removed after 2022."
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#endif
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