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c6ff132d42
A lot of header files are only used internally now, so they can be moved to mach-s3c, out of the visibility of drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200806182059.2431-40-krzk@kernel.org [krzk: Rebase and fixup leds-s3c24xx driver] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
40 lines
1 KiB
C
40 lines
1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2010 Samsung Electronics Co., Ltd.
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// http://www.samsung.com/
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//
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// S3C64XX setup information for IDE
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/platform_data/ata-samsung_cf.h>
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#include "map.h"
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#include "regs-clock.h"
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#include "gpio-cfg.h"
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#include "gpio-samsung.h"
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void s3c64xx_ide_setup_gpio(void)
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{
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u32 reg;
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reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
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/* Independent CF interface, CF chip select configuration */
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writel(reg | MEM_SYS_CFG_INDEP_CF |
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MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
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s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
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/* Set XhiDATA[15:0] pins as CF Data[15:0] */
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s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
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/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
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s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
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/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
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s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
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s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
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}
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