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2cbd1cc3dc
The integrated assembler of Clang 10 and earlier do not allow to access
the VFP registers through the coprocessor load/store instructions:
arch/arm/vfp/vfpmodule.c:342:2: error: invalid operand for instruction
fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
^
arch/arm/vfp/vfpinstr.h:79:6: note: expanded from macro 'fmxr'
asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0"
^
<inline asm>:1:6: note: instantiated into assembly here
mcr p10, 7, r0, cr8, cr0, 0 @ fmxr FPEXC, r0
^
This has been addressed with Clang 11 [0]. However, to support earlier
versions of Clang and for better readability use of VFP assembler
mnemonics still is preferred.
Ideally we would replace this code with the unified assembler language
mnemonics vmrs/vmsr on call sites along with .fpu assembler directives.
The GNU assembler supports the .fpu directive at least since 2.17 (when
documentation has been added). Since Linux requires binutils 2.21 it is
safe to use .fpu directive. However, binutils does not allow to use
FPINST or FPINST2 as an argument to vmrs/vmsr instructions up to
binutils 2.24 (see binutils commit 16d02dc907c5):
arch/arm/vfp/vfphw.S: Assembler messages:
arch/arm/vfp/vfphw.S:162: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST,r6'
arch/arm/vfp/vfphw.S:165: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST2,r8'
arch/arm/vfp/vfphw.S:235: Error: operand 1 must be a VFP extension System Register -- `vmrs r3,FPINST'
arch/arm/vfp/vfphw.S:238: Error: operand 1 must be a VFP extension System Register -- `vmrs r12,FPINST2'
Use as-instr in Kconfig to check if FPINST/FPINST2 can be used. If they
can be used make use of .fpu directives and UAL VFP mnemonics for
register access.
This allows to build vfpmodule.c with Clang and its integrated assembler.
[0] https://reviews.llvm.org/D59733
Link: https://github.com/ClangBuiltLinux/linux/issues/905
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/vfp/vfpinstr.h
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* VFP instruction masks.
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*/
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#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
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#define INST_CPRT(inst) ((inst) & (1 << 4))
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#define INST_CPRT_L(inst) ((inst) & (1 << 20))
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#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
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#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
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#define INST_CPNUM(inst) ((inst) & 0xf00)
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#define CPNUM(cp) ((cp) << 8)
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#define FOP_MASK (0x00b00040)
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#define FOP_FMAC (0x00000000)
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#define FOP_FNMAC (0x00000040)
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#define FOP_FMSC (0x00100000)
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#define FOP_FNMSC (0x00100040)
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#define FOP_FMUL (0x00200000)
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#define FOP_FNMUL (0x00200040)
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#define FOP_FADD (0x00300000)
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#define FOP_FSUB (0x00300040)
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#define FOP_FDIV (0x00800000)
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#define FOP_EXT (0x00b00040)
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#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
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#define FEXT_MASK (0x000f0080)
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#define FEXT_FCPY (0x00000000)
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#define FEXT_FABS (0x00000080)
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#define FEXT_FNEG (0x00010000)
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#define FEXT_FSQRT (0x00010080)
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#define FEXT_FCMP (0x00040000)
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#define FEXT_FCMPE (0x00040080)
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#define FEXT_FCMPZ (0x00050000)
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#define FEXT_FCMPEZ (0x00050080)
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#define FEXT_FCVT (0x00070080)
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#define FEXT_FUITO (0x00080000)
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#define FEXT_FSITO (0x00080080)
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#define FEXT_FTOUI (0x000c0000)
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#define FEXT_FTOUIZ (0x000c0080)
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#define FEXT_FTOSI (0x000d0000)
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#define FEXT_FTOSIZ (0x000d0080)
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#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
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#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
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#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
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#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
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#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
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#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
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#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
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#define FPSCR_N (1 << 31)
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#define FPSCR_Z (1 << 30)
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#define FPSCR_C (1 << 29)
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#define FPSCR_V (1 << 28)
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#ifdef CONFIG_AS_VFP_VMRS_FPINST
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm(".fpu vfpv2\n" \
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"vmrs %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmxr(_vfp_,_var_) \
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asm(".fpu vfpv2\n" \
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"vmsr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc")
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#else
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#define vfpreg(_vfp_) #_vfp_
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#define fmrx(_vfp_) ({ \
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u32 __v; \
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asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
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: "=r" (__v) : : "cc"); \
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__v; \
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})
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#define fmxr(_vfp_,_var_) \
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asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
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: : "r" (_var_) : "cc")
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#endif
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u32 vfp_single_cpdo(u32 inst, u32 fpscr);
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u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
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u32 vfp_double_cpdo(u32 inst, u32 fpscr);
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