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This is the Intel version of a confidential computing solution called Trust Domain Extensions (TDX). This series adds support to run the kernel as part of a TDX guest. It provides similar guest protections to AMD's SEV-SNP like guest memory and register state encryption, memory integrity protection and a lot more. Design-wise, it differs from AMD's solution considerably: it uses a software module which runs in a special CPU mode called (Secure Arbitration Mode) SEAM. As the name suggests, this module serves as sort of an arbiter which the confidential guest calls for services it needs during its lifetime. Just like AMD's SNP set, this series reworks and streamlines certain parts of x86 arch code so that this feature can be properly accomodated. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmKLbisACgkQEsHwGGHe VUqZLg/7B55iygCwzz0W/KLcXL2cISatUpzGbFs1XTbE9DMz06BPkOsEjF2k8ckv kfZjgqhSx3GvUI80gK0Tn2M2DfIj3nKuNSXd1pfextP7AxEf68FFJsQz1Ju7bHpT pZaG+g8IK4+mnEHEKTCO9ANg/Zw8yqJLdtsCaCNE9SUGUfQ6m/ujTEfsambXDHNm khyCAgpIGSOt51/4apoR9ebyrNCaeVbDawpIPjTy+iyFRc/WyaLFV9CQ8klw4gbw r/90x2JYxvAf0/z/ifT9Wa+TnYiQ0d4VjFbfr0iJ4GcPn5L3EIoIKPE8vPGMpoSX fLSzoNmAOT3ja57ytUUQ3o0edoRUIPEdixOebf9qWvE/aj7W37YRzrlJ8Ej/x9Jy HcI4WZF6Dr1bh6FnI/xX2eVZRzLOL4j9gNyPCwIbvgr1NjDqQnxU7nhxVMmQhJrs IdiEcP5WYerLKfka/uF//QfWUg5mDBgFa1/3xK57Z3j0iKWmgjaPpR0SWlOKjj8G tr0gGN9ejikZTqXKGsHn8fv/R3bjXvbVD8z0IEcx+MIrRmZPnX2QBlg7UA1AXV5n HoVwPFdH1QAtjZq1MRcL4hTOjz3FkS68rg7ZH0f2GWJAzWmEGytBIhECRnN/PFFq VwRB4dCCt0bzqRxkiH5lzdgR+xqRe61juQQsMzg+Flv/trpXDqM= =ac9K -----END PGP SIGNATURE----- Merge tag 'x86_tdx_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull Intel TDX support from Borislav Petkov: "Intel Trust Domain Extensions (TDX) support. This is the Intel version of a confidential computing solution called Trust Domain Extensions (TDX). This series adds support to run the kernel as part of a TDX guest. It provides similar guest protections to AMD's SEV-SNP like guest memory and register state encryption, memory integrity protection and a lot more. Design-wise, it differs from AMD's solution considerably: it uses a software module which runs in a special CPU mode called (Secure Arbitration Mode) SEAM. As the name suggests, this module serves as sort of an arbiter which the confidential guest calls for services it needs during its lifetime. Just like AMD's SNP set, this series reworks and streamlines certain parts of x86 arch code so that this feature can be properly accomodated" * tag 'x86_tdx_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) x86/tdx: Fix RETs in TDX asm x86/tdx: Annotate a noreturn function x86/mm: Fix spacing within memory encryption features message x86/kaslr: Fix build warning in KASLR code in boot stub Documentation/x86: Document TDX kernel architecture ACPICA: Avoid cache flush inside virtual machines x86/tdx/ioapic: Add shared bit for IOAPIC base address x86/mm: Make DMA memory shared for TD guest x86/mm/cpa: Add support for TDX shared memory x86/tdx: Make pages shared in ioremap() x86/topology: Disable CPU online/offline control for TDX guests x86/boot: Avoid #VE during boot for TDX platforms x86/boot: Set CR0.NE early and keep it set during the boot x86/acpi/x86/boot: Add multiprocessor wake-up support x86/boot: Add a trampoline for booting APs via firmware handoff x86/tdx: Wire up KVM hypercalls x86/tdx: Port I/O: Add early boot support x86/tdx: Port I/O: Add runtime hypercalls x86/boot: Port I/O: Add decompression-time support for TDX x86/boot: Port I/O: Allow to hook up alternative helpers ...
140 lines
3.1 KiB
C
140 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Confidential Computing Platform Capability checks
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*
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* Copyright (C) 2021 Advanced Micro Devices, Inc.
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*
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/export.h>
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#include <linux/cc_platform.h>
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#include <asm/coco.h>
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#include <asm/processor.h>
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static enum cc_vendor vendor __ro_after_init;
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static u64 cc_mask __ro_after_init;
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static bool intel_cc_platform_has(enum cc_attr attr)
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{
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switch (attr) {
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case CC_ATTR_GUEST_UNROLL_STRING_IO:
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case CC_ATTR_HOTPLUG_DISABLED:
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case CC_ATTR_GUEST_MEM_ENCRYPT:
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case CC_ATTR_MEM_ENCRYPT:
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return true;
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default:
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return false;
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}
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}
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/*
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* SME and SEV are very similar but they are not the same, so there are
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* times that the kernel will need to distinguish between SME and SEV. The
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* cc_platform_has() function is used for this. When a distinction isn't
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* needed, the CC_ATTR_MEM_ENCRYPT attribute can be used.
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*
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* The trampoline code is a good example for this requirement. Before
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* paging is activated, SME will access all memory as decrypted, but SEV
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* will access all memory as encrypted. So, when APs are being brought
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* up under SME the trampoline area cannot be encrypted, whereas under SEV
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* the trampoline area must be encrypted.
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*/
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static bool amd_cc_platform_has(enum cc_attr attr)
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{
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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switch (attr) {
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case CC_ATTR_MEM_ENCRYPT:
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return sme_me_mask;
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case CC_ATTR_HOST_MEM_ENCRYPT:
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return sme_me_mask && !(sev_status & MSR_AMD64_SEV_ENABLED);
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case CC_ATTR_GUEST_MEM_ENCRYPT:
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return sev_status & MSR_AMD64_SEV_ENABLED;
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case CC_ATTR_GUEST_STATE_ENCRYPT:
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return sev_status & MSR_AMD64_SEV_ES_ENABLED;
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/*
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* With SEV, the rep string I/O instructions need to be unrolled
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* but SEV-ES supports them through the #VC handler.
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*/
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case CC_ATTR_GUEST_UNROLL_STRING_IO:
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return (sev_status & MSR_AMD64_SEV_ENABLED) &&
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!(sev_status & MSR_AMD64_SEV_ES_ENABLED);
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case CC_ATTR_GUEST_SEV_SNP:
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return sev_status & MSR_AMD64_SEV_SNP_ENABLED;
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default:
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return false;
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}
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#else
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return false;
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#endif
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}
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static bool hyperv_cc_platform_has(enum cc_attr attr)
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{
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return attr == CC_ATTR_GUEST_MEM_ENCRYPT;
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}
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bool cc_platform_has(enum cc_attr attr)
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{
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switch (vendor) {
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case CC_VENDOR_AMD:
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return amd_cc_platform_has(attr);
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case CC_VENDOR_INTEL:
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return intel_cc_platform_has(attr);
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case CC_VENDOR_HYPERV:
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return hyperv_cc_platform_has(attr);
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default:
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return false;
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}
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}
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EXPORT_SYMBOL_GPL(cc_platform_has);
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u64 cc_mkenc(u64 val)
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{
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/*
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* Both AMD and Intel use a bit in the page table to indicate
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* encryption status of the page.
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*
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* - for AMD, bit *set* means the page is encrypted
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* - for Intel *clear* means encrypted.
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*/
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switch (vendor) {
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case CC_VENDOR_AMD:
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return val | cc_mask;
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case CC_VENDOR_INTEL:
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return val & ~cc_mask;
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default:
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return val;
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}
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}
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u64 cc_mkdec(u64 val)
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{
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/* See comment in cc_mkenc() */
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switch (vendor) {
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case CC_VENDOR_AMD:
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return val & ~cc_mask;
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case CC_VENDOR_INTEL:
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return val | cc_mask;
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default:
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return val;
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}
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}
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EXPORT_SYMBOL_GPL(cc_mkdec);
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__init void cc_set_vendor(enum cc_vendor v)
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{
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vendor = v;
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}
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__init void cc_set_mask(u64 mask)
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{
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cc_mask = mask;
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}
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