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![Vitaly Kuznetsov](/assets/img/avatar_default.png)
__send_ipi_mask_ex() uses an optimization: when the target CPU mask is
equal to 'cpu_present_mask' it uses 'HV_GENERIC_SET_ALL' format to avoid
converting the specified cpumask to VP_SET. This case was overlooked when
'exclude_self' parameter was added. As the result, a spurious IPI to
'self' can be send.
Reported-by: Thomas Gleixner <tglx@linutronix.de>
Fixes: dfb5c1e12c
("x86/hyperv: remove on-stack cpumask from hv_send_ipi_mask_allbutself")
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/20211006125016.941616-1-vkuznets@redhat.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
317 lines
7.9 KiB
C
317 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Hyper-V specific APIC code.
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*
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* Copyright (C) 2018, Microsoft, Inc.
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*
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* Author : K. Y. Srinivasan <kys@microsoft.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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*/
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#include <linux/types.h>
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#include <linux/vmalloc.h>
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#include <linux/mm.h>
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#include <linux/clockchips.h>
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#include <linux/hyperv.h>
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#include <linux/slab.h>
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#include <linux/cpuhotplug.h>
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#include <asm/hypervisor.h>
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#include <asm/mshyperv.h>
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#include <asm/apic.h>
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#include <asm/trace/hyperv.h>
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static struct apic orig_apic;
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static u64 hv_apic_icr_read(void)
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{
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u64 reg_val;
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rdmsrl(HV_X64_MSR_ICR, reg_val);
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return reg_val;
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}
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static void hv_apic_icr_write(u32 low, u32 id)
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{
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u64 reg_val;
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reg_val = SET_APIC_DEST_FIELD(id);
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reg_val = reg_val << 32;
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reg_val |= low;
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wrmsrl(HV_X64_MSR_ICR, reg_val);
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}
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static u32 hv_apic_read(u32 reg)
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{
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u32 reg_val, hi;
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switch (reg) {
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case APIC_EOI:
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rdmsr(HV_X64_MSR_EOI, reg_val, hi);
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(void)hi;
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return reg_val;
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case APIC_TASKPRI:
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rdmsr(HV_X64_MSR_TPR, reg_val, hi);
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(void)hi;
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return reg_val;
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default:
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return native_apic_mem_read(reg);
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}
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}
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static void hv_apic_write(u32 reg, u32 val)
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{
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switch (reg) {
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case APIC_EOI:
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wrmsr(HV_X64_MSR_EOI, val, 0);
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break;
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case APIC_TASKPRI:
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wrmsr(HV_X64_MSR_TPR, val, 0);
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break;
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default:
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native_apic_mem_write(reg, val);
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}
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}
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static void hv_apic_eoi_write(u32 reg, u32 val)
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{
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struct hv_vp_assist_page *hvp = hv_vp_assist_page[smp_processor_id()];
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if (hvp && (xchg(&hvp->apic_assist, 0) & 0x1))
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return;
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wrmsr(HV_X64_MSR_EOI, val, 0);
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}
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/*
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* IPI implementation on Hyper-V.
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*/
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static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector,
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bool exclude_self)
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{
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struct hv_send_ipi_ex **arg;
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struct hv_send_ipi_ex *ipi_arg;
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unsigned long flags;
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int nr_bank = 0;
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u64 status = HV_STATUS_INVALID_PARAMETER;
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if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
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return false;
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local_irq_save(flags);
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arg = (struct hv_send_ipi_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
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ipi_arg = *arg;
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if (unlikely(!ipi_arg))
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goto ipi_mask_ex_done;
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ipi_arg->vector = vector;
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ipi_arg->reserved = 0;
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ipi_arg->vp_set.valid_bank_mask = 0;
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/*
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* Use HV_GENERIC_SET_ALL and avoid converting cpumask to VP_SET
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* when the IPI is sent to all currently present CPUs.
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*/
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if (!cpumask_equal(mask, cpu_present_mask) || exclude_self) {
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ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
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if (exclude_self)
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nr_bank = cpumask_to_vpset_noself(&(ipi_arg->vp_set), mask);
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else
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nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
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/*
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* 'nr_bank <= 0' means some CPUs in cpumask can't be
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* represented in VP_SET. Return an error and fall back to
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* native (architectural) method of sending IPIs.
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*/
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if (nr_bank <= 0)
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goto ipi_mask_ex_done;
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} else {
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ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
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}
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status = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
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ipi_arg, NULL);
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ipi_mask_ex_done:
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local_irq_restore(flags);
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return hv_result_success(status);
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}
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static bool __send_ipi_mask(const struct cpumask *mask, int vector,
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bool exclude_self)
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{
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int cur_cpu, vcpu, this_cpu = smp_processor_id();
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struct hv_send_ipi ipi_arg;
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u64 status;
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unsigned int weight;
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trace_hyperv_send_ipi_mask(mask, vector);
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weight = cpumask_weight(mask);
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/*
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* Do nothing if
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* 1. the mask is empty
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* 2. the mask only contains self when exclude_self is true
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*/
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if (weight == 0 ||
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(exclude_self && weight == 1 && cpumask_test_cpu(this_cpu, mask)))
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return true;
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if (!hv_hypercall_pg)
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return false;
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if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
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return false;
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/*
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* From the supplied CPU set we need to figure out if we can get away
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* with cheaper HVCALL_SEND_IPI hypercall. This is possible when the
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* highest VP number in the set is < 64. As VP numbers are usually in
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* ascending order and match Linux CPU ids, here is an optimization:
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* we check the VP number for the highest bit in the supplied set first
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* so we can quickly find out if using HVCALL_SEND_IPI_EX hypercall is
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* a must. We will also check all VP numbers when walking the supplied
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* CPU set to remain correct in all cases.
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*/
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if (hv_cpu_number_to_vp_number(cpumask_last(mask)) >= 64)
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goto do_ex_hypercall;
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ipi_arg.vector = vector;
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ipi_arg.cpu_mask = 0;
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for_each_cpu(cur_cpu, mask) {
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if (exclude_self && cur_cpu == this_cpu)
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continue;
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vcpu = hv_cpu_number_to_vp_number(cur_cpu);
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if (vcpu == VP_INVAL)
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return false;
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/*
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* This particular version of the IPI hypercall can
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* only target upto 64 CPUs.
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*/
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if (vcpu >= 64)
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goto do_ex_hypercall;
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__set_bit(vcpu, (unsigned long *)&ipi_arg.cpu_mask);
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}
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status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, ipi_arg.vector,
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ipi_arg.cpu_mask);
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return hv_result_success(status);
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do_ex_hypercall:
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return __send_ipi_mask_ex(mask, vector, exclude_self);
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}
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static bool __send_ipi_one(int cpu, int vector)
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{
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int vp = hv_cpu_number_to_vp_number(cpu);
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u64 status;
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trace_hyperv_send_ipi_one(cpu, vector);
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if (!hv_hypercall_pg || (vp == VP_INVAL))
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return false;
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if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
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return false;
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if (vp >= 64)
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return __send_ipi_mask_ex(cpumask_of(cpu), vector, false);
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status = hv_do_fast_hypercall16(HVCALL_SEND_IPI, vector, BIT_ULL(vp));
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return hv_result_success(status);
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}
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static void hv_send_ipi(int cpu, int vector)
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{
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if (!__send_ipi_one(cpu, vector))
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orig_apic.send_IPI(cpu, vector);
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}
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static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
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{
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if (!__send_ipi_mask(mask, vector, false))
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orig_apic.send_IPI_mask(mask, vector);
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}
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static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
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{
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if (!__send_ipi_mask(mask, vector, true))
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orig_apic.send_IPI_mask_allbutself(mask, vector);
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}
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static void hv_send_ipi_allbutself(int vector)
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{
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hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
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}
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static void hv_send_ipi_all(int vector)
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{
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if (!__send_ipi_mask(cpu_online_mask, vector, false))
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orig_apic.send_IPI_all(vector);
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}
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static void hv_send_ipi_self(int vector)
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{
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if (!__send_ipi_one(smp_processor_id(), vector))
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orig_apic.send_IPI_self(vector);
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}
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void __init hv_apic_init(void)
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{
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if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
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pr_info("Hyper-V: Using IPI hypercalls\n");
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/*
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* Set the IPI entry points.
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*/
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orig_apic = *apic;
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apic->send_IPI = hv_send_ipi;
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apic->send_IPI_mask = hv_send_ipi_mask;
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apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
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apic->send_IPI_allbutself = hv_send_ipi_allbutself;
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apic->send_IPI_all = hv_send_ipi_all;
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apic->send_IPI_self = hv_send_ipi_self;
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}
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if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
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pr_info("Hyper-V: Using enlightened APIC (%s mode)",
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x2apic_enabled() ? "x2apic" : "xapic");
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/*
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* When in x2apic mode, don't use the Hyper-V specific APIC
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* accessors since the field layout in the ICR register is
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* different in x2apic mode. Furthermore, the architectural
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* x2apic MSRs function just as well as the Hyper-V
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* synthetic APIC MSRs, so there's no benefit in having
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* separate Hyper-V accessors for x2apic mode. The only
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* exception is hv_apic_eoi_write, because it benefits from
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* lazy EOI when available, but the same accessor works for
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* both xapic and x2apic because the field layout is the same.
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*/
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apic_set_eoi_write(hv_apic_eoi_write);
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if (!x2apic_enabled()) {
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apic->read = hv_apic_read;
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apic->write = hv_apic_write;
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apic->icr_write = hv_apic_icr_write;
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apic->icr_read = hv_apic_icr_read;
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}
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}
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}
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