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![Jinrong Liang](/assets/img/avatar_default.png)
The "unsigned long addr" and "unsigned long length" parameter of ioapic_read_indirect() is not used, so remove it. No functional change intended. Signed-off-by: Jinrong Liang <cloudliang@tencent.com> Message-Id: <20220125095909.38122-14-cloudliang@tencent.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
745 lines
20 KiB
C
745 lines
20 KiB
C
/*
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* Copyright (C) 2001 MandrakeSoft S.A.
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*
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* MandrakeSoft S.A.
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* 43, rue d'Aboukir
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* 75002 Paris - France
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* http://www.linux-mandrake.com/
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* http://www.mandrakesoft.com/
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Yunhong Jiang <yunhong.jiang@intel.com>
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* Yaozu (Eddie) Dong <eddie.dong@intel.com>
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* Based on Xen 3.1 code.
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*/
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <linux/mm.h>
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#include <linux/highmem.h>
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#include <linux/smp.h>
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#include <linux/hrtimer.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/nospec.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/current.h>
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#include <trace/events/kvm.h>
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#include "ioapic.h"
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#include "lapic.h"
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#include "irq.h"
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static int ioapic_service(struct kvm_ioapic *vioapic, int irq,
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bool line_status);
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static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
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struct kvm_ioapic *ioapic,
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int trigger_mode,
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int pin);
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static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic)
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{
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unsigned long result = 0;
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
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| (IOAPIC_VERSION_ID & 0xff));
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break;
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case IOAPIC_REG_APIC_ID:
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case IOAPIC_REG_ARB_ID:
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result = ((ioapic->id & 0xf) << 24);
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break;
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default:
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{
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u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
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u64 redir_content = ~0ULL;
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if (redir_index < IOAPIC_NUM_PINS) {
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u32 index = array_index_nospec(
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redir_index, IOAPIC_NUM_PINS);
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redir_content = ioapic->redirtbl[index].bits;
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}
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result = (ioapic->ioregsel & 0x1) ?
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(redir_content >> 32) & 0xffffffff :
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redir_content & 0xffffffff;
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break;
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}
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}
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return result;
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}
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static void rtc_irq_eoi_tracking_reset(struct kvm_ioapic *ioapic)
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{
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ioapic->rtc_status.pending_eoi = 0;
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bitmap_zero(ioapic->rtc_status.dest_map.map, KVM_MAX_VCPU_IDS);
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}
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static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic);
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static void rtc_status_pending_eoi_check_valid(struct kvm_ioapic *ioapic)
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{
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if (WARN_ON(ioapic->rtc_status.pending_eoi < 0))
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kvm_rtc_eoi_tracking_restore_all(ioapic);
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}
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static void __rtc_irq_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
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{
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bool new_val, old_val;
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
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union kvm_ioapic_redirect_entry *e;
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e = &ioapic->redirtbl[RTC_GSI];
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if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
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e->fields.dest_id,
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kvm_lapic_irq_dest_mode(!!e->fields.dest_mode)))
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return;
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new_val = kvm_apic_pending_eoi(vcpu, e->fields.vector);
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old_val = test_bit(vcpu->vcpu_id, dest_map->map);
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if (new_val == old_val)
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return;
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if (new_val) {
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__set_bit(vcpu->vcpu_id, dest_map->map);
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dest_map->vectors[vcpu->vcpu_id] = e->fields.vector;
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ioapic->rtc_status.pending_eoi++;
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} else {
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__clear_bit(vcpu->vcpu_id, dest_map->map);
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ioapic->rtc_status.pending_eoi--;
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rtc_status_pending_eoi_check_valid(ioapic);
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}
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}
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void kvm_rtc_eoi_tracking_restore_one(struct kvm_vcpu *vcpu)
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{
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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spin_lock(&ioapic->lock);
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__rtc_irq_eoi_tracking_restore_one(vcpu);
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spin_unlock(&ioapic->lock);
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}
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static void kvm_rtc_eoi_tracking_restore_all(struct kvm_ioapic *ioapic)
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{
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struct kvm_vcpu *vcpu;
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unsigned long i;
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if (RTC_GSI >= IOAPIC_NUM_PINS)
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return;
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rtc_irq_eoi_tracking_reset(ioapic);
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kvm_for_each_vcpu(i, vcpu, ioapic->kvm)
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__rtc_irq_eoi_tracking_restore_one(vcpu);
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}
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static void rtc_irq_eoi(struct kvm_ioapic *ioapic, struct kvm_vcpu *vcpu,
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int vector)
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{
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struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
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/* RTC special handling */
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if (test_bit(vcpu->vcpu_id, dest_map->map) &&
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(vector == dest_map->vectors[vcpu->vcpu_id]) &&
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(test_and_clear_bit(vcpu->vcpu_id,
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ioapic->rtc_status.dest_map.map))) {
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--ioapic->rtc_status.pending_eoi;
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rtc_status_pending_eoi_check_valid(ioapic);
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}
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}
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static bool rtc_irq_check_coalesced(struct kvm_ioapic *ioapic)
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{
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if (ioapic->rtc_status.pending_eoi > 0)
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return true; /* coalesced */
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return false;
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}
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static void ioapic_lazy_update_eoi(struct kvm_ioapic *ioapic, int irq)
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{
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unsigned long i;
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struct kvm_vcpu *vcpu;
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union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
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kvm_for_each_vcpu(i, vcpu, ioapic->kvm) {
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if (!kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
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entry->fields.dest_id,
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entry->fields.dest_mode) ||
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kvm_apic_pending_eoi(vcpu, entry->fields.vector))
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continue;
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/*
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* If no longer has pending EOI in LAPICs, update
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* EOI for this vector.
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*/
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rtc_irq_eoi(ioapic, vcpu, entry->fields.vector);
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break;
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}
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}
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static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
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int irq_level, bool line_status)
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{
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union kvm_ioapic_redirect_entry entry;
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u32 mask = 1 << irq;
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u32 old_irr;
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int edge, ret;
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entry = ioapic->redirtbl[irq];
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edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
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if (!irq_level) {
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ioapic->irr &= ~mask;
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ret = 1;
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goto out;
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}
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/*
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* AMD SVM AVIC accelerate EOI write iff the interrupt is edge
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* triggered, in which case the in-kernel IOAPIC will not be able
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* to receive the EOI. In this case, we do a lazy update of the
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* pending EOI when trying to set IOAPIC irq.
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*/
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if (edge && kvm_apicv_activated(ioapic->kvm))
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ioapic_lazy_update_eoi(ioapic, irq);
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/*
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* Return 0 for coalesced interrupts; for edge-triggered interrupts,
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* this only happens if a previous edge has not been delivered due
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* to masking. For level interrupts, the remote_irr field tells
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* us if the interrupt is waiting for an EOI.
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*
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* RTC is special: it is edge-triggered, but userspace likes to know
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* if it has been already ack-ed via EOI because coalesced RTC
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* interrupts lead to time drift in Windows guests. So we track
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* EOI manually for the RTC interrupt.
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*/
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if (irq == RTC_GSI && line_status &&
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rtc_irq_check_coalesced(ioapic)) {
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ret = 0;
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goto out;
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}
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old_irr = ioapic->irr;
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ioapic->irr |= mask;
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if (edge) {
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ioapic->irr_delivered &= ~mask;
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if (old_irr == ioapic->irr) {
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ret = 0;
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goto out;
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}
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}
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ret = ioapic_service(ioapic, irq, line_status);
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out:
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trace_kvm_ioapic_set_irq(entry.bits, irq, ret == 0);
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return ret;
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}
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static void kvm_ioapic_inject_all(struct kvm_ioapic *ioapic, unsigned long irr)
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{
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u32 idx;
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rtc_irq_eoi_tracking_reset(ioapic);
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for_each_set_bit(idx, &irr, IOAPIC_NUM_PINS)
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ioapic_set_irq(ioapic, idx, 1, true);
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kvm_rtc_eoi_tracking_restore_all(ioapic);
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}
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void kvm_ioapic_scan_entry(struct kvm_vcpu *vcpu, ulong *ioapic_handled_vectors)
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{
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struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
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struct dest_map *dest_map = &ioapic->rtc_status.dest_map;
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union kvm_ioapic_redirect_entry *e;
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int index;
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spin_lock(&ioapic->lock);
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/* Make sure we see any missing RTC EOI */
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if (test_bit(vcpu->vcpu_id, dest_map->map))
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__set_bit(dest_map->vectors[vcpu->vcpu_id],
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ioapic_handled_vectors);
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for (index = 0; index < IOAPIC_NUM_PINS; index++) {
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e = &ioapic->redirtbl[index];
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if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG ||
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kvm_irq_has_notifier(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index) ||
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index == RTC_GSI) {
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u16 dm = kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
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if (kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
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e->fields.dest_id, dm) ||
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kvm_apic_pending_eoi(vcpu, e->fields.vector))
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__set_bit(e->fields.vector,
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ioapic_handled_vectors);
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}
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}
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spin_unlock(&ioapic->lock);
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}
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void kvm_arch_post_irq_ack_notifier_list_update(struct kvm *kvm)
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{
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if (!ioapic_in_kernel(kvm))
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return;
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kvm_make_scan_ioapic_request(kvm);
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}
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static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
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{
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unsigned index;
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bool mask_before, mask_after;
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union kvm_ioapic_redirect_entry *e;
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int old_remote_irr, old_delivery_status, old_dest_id, old_dest_mode;
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DECLARE_BITMAP(vcpu_bitmap, KVM_MAX_VCPUS);
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switch (ioapic->ioregsel) {
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case IOAPIC_REG_VERSION:
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/* Writes are ignored. */
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break;
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case IOAPIC_REG_APIC_ID:
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ioapic->id = (val >> 24) & 0xf;
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break;
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case IOAPIC_REG_ARB_ID:
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break;
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default:
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index = (ioapic->ioregsel - 0x10) >> 1;
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if (index >= IOAPIC_NUM_PINS)
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return;
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index = array_index_nospec(index, IOAPIC_NUM_PINS);
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e = &ioapic->redirtbl[index];
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mask_before = e->fields.mask;
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/* Preserve read-only fields */
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old_remote_irr = e->fields.remote_irr;
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old_delivery_status = e->fields.delivery_status;
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old_dest_id = e->fields.dest_id;
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old_dest_mode = e->fields.dest_mode;
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if (ioapic->ioregsel & 1) {
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e->bits &= 0xffffffff;
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e->bits |= (u64) val << 32;
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} else {
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e->bits &= ~0xffffffffULL;
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e->bits |= (u32) val;
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}
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e->fields.remote_irr = old_remote_irr;
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e->fields.delivery_status = old_delivery_status;
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/*
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* Some OSes (Linux, Xen) assume that Remote IRR bit will
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* be cleared by IOAPIC hardware when the entry is configured
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* as edge-triggered. This behavior is used to simulate an
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* explicit EOI on IOAPICs that don't have the EOI register.
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*/
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if (e->fields.trig_mode == IOAPIC_EDGE_TRIG)
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e->fields.remote_irr = 0;
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mask_after = e->fields.mask;
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if (mask_before != mask_after)
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kvm_fire_mask_notifiers(ioapic->kvm, KVM_IRQCHIP_IOAPIC, index, mask_after);
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if (e->fields.trig_mode == IOAPIC_LEVEL_TRIG
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&& ioapic->irr & (1 << index))
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ioapic_service(ioapic, index, false);
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if (e->fields.delivery_mode == APIC_DM_FIXED) {
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struct kvm_lapic_irq irq;
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irq.vector = e->fields.vector;
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irq.delivery_mode = e->fields.delivery_mode << 8;
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irq.dest_mode =
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kvm_lapic_irq_dest_mode(!!e->fields.dest_mode);
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irq.level = false;
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irq.trig_mode = e->fields.trig_mode;
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irq.shorthand = APIC_DEST_NOSHORT;
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irq.dest_id = e->fields.dest_id;
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irq.msi_redir_hint = false;
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bitmap_zero(vcpu_bitmap, KVM_MAX_VCPUS);
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kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
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vcpu_bitmap);
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if (old_dest_mode != e->fields.dest_mode ||
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old_dest_id != e->fields.dest_id) {
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/*
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* Update vcpu_bitmap with vcpus specified in
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* the previous request as well. This is done to
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* keep ioapic_handled_vectors synchronized.
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*/
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irq.dest_id = old_dest_id;
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irq.dest_mode =
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kvm_lapic_irq_dest_mode(
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!!e->fields.dest_mode);
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kvm_bitmap_or_dest_vcpus(ioapic->kvm, &irq,
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vcpu_bitmap);
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}
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kvm_make_scan_ioapic_request_mask(ioapic->kvm,
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vcpu_bitmap);
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} else {
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kvm_make_scan_ioapic_request(ioapic->kvm);
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}
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break;
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}
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}
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static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
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{
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union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
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struct kvm_lapic_irq irqe;
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int ret;
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if (entry->fields.mask ||
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(entry->fields.trig_mode == IOAPIC_LEVEL_TRIG &&
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entry->fields.remote_irr))
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return -1;
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irqe.dest_id = entry->fields.dest_id;
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irqe.vector = entry->fields.vector;
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irqe.dest_mode = kvm_lapic_irq_dest_mode(!!entry->fields.dest_mode);
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irqe.trig_mode = entry->fields.trig_mode;
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irqe.delivery_mode = entry->fields.delivery_mode << 8;
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irqe.level = 1;
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irqe.shorthand = APIC_DEST_NOSHORT;
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irqe.msi_redir_hint = false;
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if (irqe.trig_mode == IOAPIC_EDGE_TRIG)
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ioapic->irr_delivered |= 1 << irq;
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if (irq == RTC_GSI && line_status) {
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/*
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* pending_eoi cannot ever become negative (see
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* rtc_status_pending_eoi_check_valid) and the caller
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* ensures that it is only called if it is >= zero, namely
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* if rtc_irq_check_coalesced returns false).
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*/
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BUG_ON(ioapic->rtc_status.pending_eoi != 0);
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ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe,
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&ioapic->rtc_status.dest_map);
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ioapic->rtc_status.pending_eoi = (ret < 0 ? 0 : ret);
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} else
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ret = kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe, NULL);
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if (ret && irqe.trig_mode == IOAPIC_LEVEL_TRIG)
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entry->fields.remote_irr = 1;
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return ret;
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}
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
|
|
int level, bool line_status)
|
|
{
|
|
int ret, irq_level;
|
|
|
|
BUG_ON(irq < 0 || irq >= IOAPIC_NUM_PINS);
|
|
|
|
spin_lock(&ioapic->lock);
|
|
irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
|
|
irq_source_id, level);
|
|
ret = ioapic_set_irq(ioapic, irq, irq_level, line_status);
|
|
|
|
spin_unlock(&ioapic->lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
|
|
{
|
|
int i;
|
|
|
|
spin_lock(&ioapic->lock);
|
|
for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
|
|
__clear_bit(irq_source_id, &ioapic->irq_states[i]);
|
|
spin_unlock(&ioapic->lock);
|
|
}
|
|
|
|
static void kvm_ioapic_eoi_inject_work(struct work_struct *work)
|
|
{
|
|
int i;
|
|
struct kvm_ioapic *ioapic = container_of(work, struct kvm_ioapic,
|
|
eoi_inject.work);
|
|
spin_lock(&ioapic->lock);
|
|
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
|
|
union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
|
|
|
|
if (ent->fields.trig_mode != IOAPIC_LEVEL_TRIG)
|
|
continue;
|
|
|
|
if (ioapic->irr & (1 << i) && !ent->fields.remote_irr)
|
|
ioapic_service(ioapic, i, false);
|
|
}
|
|
spin_unlock(&ioapic->lock);
|
|
}
|
|
|
|
#define IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT 10000
|
|
static void kvm_ioapic_update_eoi_one(struct kvm_vcpu *vcpu,
|
|
struct kvm_ioapic *ioapic,
|
|
int trigger_mode,
|
|
int pin)
|
|
{
|
|
struct kvm_lapic *apic = vcpu->arch.apic;
|
|
union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[pin];
|
|
|
|
/*
|
|
* We are dropping lock while calling ack notifiers because ack
|
|
* notifier callbacks for assigned devices call into IOAPIC
|
|
* recursively. Since remote_irr is cleared only after call
|
|
* to notifiers if the same vector will be delivered while lock
|
|
* is dropped it will be put into irr and will be delivered
|
|
* after ack notifier returns.
|
|
*/
|
|
spin_unlock(&ioapic->lock);
|
|
kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
|
|
spin_lock(&ioapic->lock);
|
|
|
|
if (trigger_mode != IOAPIC_LEVEL_TRIG ||
|
|
kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)
|
|
return;
|
|
|
|
ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
|
|
ent->fields.remote_irr = 0;
|
|
if (!ent->fields.mask && (ioapic->irr & (1 << pin))) {
|
|
++ioapic->irq_eoi[pin];
|
|
if (ioapic->irq_eoi[pin] == IOAPIC_SUCCESSIVE_IRQ_MAX_COUNT) {
|
|
/*
|
|
* Real hardware does not deliver the interrupt
|
|
* immediately during eoi broadcast, and this
|
|
* lets a buggy guest make slow progress
|
|
* even if it does not correctly handle a
|
|
* level-triggered interrupt. Emulate this
|
|
* behavior if we detect an interrupt storm.
|
|
*/
|
|
schedule_delayed_work(&ioapic->eoi_inject, HZ / 100);
|
|
ioapic->irq_eoi[pin] = 0;
|
|
trace_kvm_ioapic_delayed_eoi_inj(ent->bits);
|
|
} else {
|
|
ioapic_service(ioapic, pin, false);
|
|
}
|
|
} else {
|
|
ioapic->irq_eoi[pin] = 0;
|
|
}
|
|
}
|
|
|
|
void kvm_ioapic_update_eoi(struct kvm_vcpu *vcpu, int vector, int trigger_mode)
|
|
{
|
|
int i;
|
|
struct kvm_ioapic *ioapic = vcpu->kvm->arch.vioapic;
|
|
|
|
spin_lock(&ioapic->lock);
|
|
rtc_irq_eoi(ioapic, vcpu, vector);
|
|
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
|
|
union kvm_ioapic_redirect_entry *ent = &ioapic->redirtbl[i];
|
|
|
|
if (ent->fields.vector != vector)
|
|
continue;
|
|
kvm_ioapic_update_eoi_one(vcpu, ioapic, trigger_mode, i);
|
|
}
|
|
spin_unlock(&ioapic->lock);
|
|
}
|
|
|
|
static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
|
|
{
|
|
return container_of(dev, struct kvm_ioapic, dev);
|
|
}
|
|
|
|
static inline int ioapic_in_range(struct kvm_ioapic *ioapic, gpa_t addr)
|
|
{
|
|
return ((addr >= ioapic->base_address &&
|
|
(addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
|
|
}
|
|
|
|
static int ioapic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
|
|
gpa_t addr, int len, void *val)
|
|
{
|
|
struct kvm_ioapic *ioapic = to_ioapic(this);
|
|
u32 result;
|
|
if (!ioapic_in_range(ioapic, addr))
|
|
return -EOPNOTSUPP;
|
|
|
|
ASSERT(!(addr & 0xf)); /* check alignment */
|
|
|
|
addr &= 0xff;
|
|
spin_lock(&ioapic->lock);
|
|
switch (addr) {
|
|
case IOAPIC_REG_SELECT:
|
|
result = ioapic->ioregsel;
|
|
break;
|
|
|
|
case IOAPIC_REG_WINDOW:
|
|
result = ioapic_read_indirect(ioapic);
|
|
break;
|
|
|
|
default:
|
|
result = 0;
|
|
break;
|
|
}
|
|
spin_unlock(&ioapic->lock);
|
|
|
|
switch (len) {
|
|
case 8:
|
|
*(u64 *) val = result;
|
|
break;
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
memcpy(val, (char *)&result, len);
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING "ioapic: wrong length %d\n", len);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int ioapic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
|
|
gpa_t addr, int len, const void *val)
|
|
{
|
|
struct kvm_ioapic *ioapic = to_ioapic(this);
|
|
u32 data;
|
|
if (!ioapic_in_range(ioapic, addr))
|
|
return -EOPNOTSUPP;
|
|
|
|
ASSERT(!(addr & 0xf)); /* check alignment */
|
|
|
|
switch (len) {
|
|
case 8:
|
|
case 4:
|
|
data = *(u32 *) val;
|
|
break;
|
|
case 2:
|
|
data = *(u16 *) val;
|
|
break;
|
|
case 1:
|
|
data = *(u8 *) val;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
|
|
return 0;
|
|
}
|
|
|
|
addr &= 0xff;
|
|
spin_lock(&ioapic->lock);
|
|
switch (addr) {
|
|
case IOAPIC_REG_SELECT:
|
|
ioapic->ioregsel = data & 0xFF; /* 8-bit register */
|
|
break;
|
|
|
|
case IOAPIC_REG_WINDOW:
|
|
ioapic_write_indirect(ioapic, data);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
spin_unlock(&ioapic->lock);
|
|
return 0;
|
|
}
|
|
|
|
static void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
|
|
{
|
|
int i;
|
|
|
|
cancel_delayed_work_sync(&ioapic->eoi_inject);
|
|
for (i = 0; i < IOAPIC_NUM_PINS; i++)
|
|
ioapic->redirtbl[i].fields.mask = 1;
|
|
ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
|
|
ioapic->ioregsel = 0;
|
|
ioapic->irr = 0;
|
|
ioapic->irr_delivered = 0;
|
|
ioapic->id = 0;
|
|
memset(ioapic->irq_eoi, 0x00, sizeof(ioapic->irq_eoi));
|
|
rtc_irq_eoi_tracking_reset(ioapic);
|
|
}
|
|
|
|
static const struct kvm_io_device_ops ioapic_mmio_ops = {
|
|
.read = ioapic_mmio_read,
|
|
.write = ioapic_mmio_write,
|
|
};
|
|
|
|
int kvm_ioapic_init(struct kvm *kvm)
|
|
{
|
|
struct kvm_ioapic *ioapic;
|
|
int ret;
|
|
|
|
ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL_ACCOUNT);
|
|
if (!ioapic)
|
|
return -ENOMEM;
|
|
spin_lock_init(&ioapic->lock);
|
|
INIT_DELAYED_WORK(&ioapic->eoi_inject, kvm_ioapic_eoi_inject_work);
|
|
kvm->arch.vioapic = ioapic;
|
|
kvm_ioapic_reset(ioapic);
|
|
kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
|
|
ioapic->kvm = kvm;
|
|
mutex_lock(&kvm->slots_lock);
|
|
ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, ioapic->base_address,
|
|
IOAPIC_MEM_LENGTH, &ioapic->dev);
|
|
mutex_unlock(&kvm->slots_lock);
|
|
if (ret < 0) {
|
|
kvm->arch.vioapic = NULL;
|
|
kfree(ioapic);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void kvm_ioapic_destroy(struct kvm *kvm)
|
|
{
|
|
struct kvm_ioapic *ioapic = kvm->arch.vioapic;
|
|
|
|
if (!ioapic)
|
|
return;
|
|
|
|
cancel_delayed_work_sync(&ioapic->eoi_inject);
|
|
mutex_lock(&kvm->slots_lock);
|
|
kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS, &ioapic->dev);
|
|
mutex_unlock(&kvm->slots_lock);
|
|
kvm->arch.vioapic = NULL;
|
|
kfree(ioapic);
|
|
}
|
|
|
|
void kvm_get_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
|
|
{
|
|
struct kvm_ioapic *ioapic = kvm->arch.vioapic;
|
|
|
|
spin_lock(&ioapic->lock);
|
|
memcpy(state, ioapic, sizeof(struct kvm_ioapic_state));
|
|
state->irr &= ~ioapic->irr_delivered;
|
|
spin_unlock(&ioapic->lock);
|
|
}
|
|
|
|
void kvm_set_ioapic(struct kvm *kvm, struct kvm_ioapic_state *state)
|
|
{
|
|
struct kvm_ioapic *ioapic = kvm->arch.vioapic;
|
|
|
|
spin_lock(&ioapic->lock);
|
|
memcpy(ioapic, state, sizeof(struct kvm_ioapic_state));
|
|
ioapic->irr = 0;
|
|
ioapic->irr_delivered = 0;
|
|
kvm_make_scan_ioapic_request(kvm);
|
|
kvm_ioapic_inject_all(ioapic, state->irr);
|
|
spin_unlock(&ioapic->lock);
|
|
}
|