mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
* ultravisor communication device driver * fix TEID on terminating storage key ops RISC-V: * Added Sv57x4 support for G-stage page table * Added range based local HFENCE functions * Added remote HFENCE functions based on VCPU requests * Added ISA extension registers in ONE_REG interface * Updated KVM RISC-V maintainers entry to cover selftests support ARM: * Add support for the ARMv8.6 WFxT extension * Guard pages for the EL2 stacks * Trap and emulate AArch32 ID registers to hide unsupported features * Ability to select and save/restore the set of hypercalls exposed to the guest * Support for PSCI-initiated suspend in collaboration with userspace * GICv3 register-based LPI invalidation support * Move host PMU event merging into the vcpu data structure * GICv3 ITS save/restore fixes * The usual set of small-scale cleanups and fixes x86: * New ioctls to get/set TSC frequency for a whole VM * Allow userspace to opt out of hypercall patching * Only do MSR filtering for MSRs accessed by rdmsr/wrmsr AMD SEV improvements: * Add KVM_EXIT_SHUTDOWN metadata for SEV-ES * V_TSC_AUX support Nested virtualization improvements for AMD: * Support for "nested nested" optimizations (nested vVMLOAD/VMSAVE, nested vGIF) * Allow AVIC to co-exist with a nested guest running * Fixes for LBR virtualizations when a nested guest is running, and nested LBR virtualization support * PAUSE filtering for nested hypervisors Guest support: * Decoupling of vcpu_is_preempted from PV spinlocks -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmKN9M4UHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNLeAf+KizAlQwxEehHHeNyTkZuKyMawrD6 zsqAENR6i1TxiXe7fDfPFbO2NR0ZulQopHbD9mwnHJ+nNw0J4UT7g3ii1IAVcXPu rQNRGMVWiu54jt+lep8/gDg0JvPGKVVKLhxUaU1kdWT9PhIOC6lwpP3vmeWkUfRi PFL/TMT0M8Nfryi0zHB0tXeqg41BiXfqO8wMySfBAHUbpv8D53D2eXQL6YlMM0pL 2quB1HxHnpueE5vj3WEPQ3PCdy1M2MTfCDBJAbZGG78Ljx45FxSGoQcmiBpPnhJr C6UGP4ZDWpml5YULUoA70k5ylCbP+vI61U4vUtzEiOjHugpPV5wFKtx5nw== =ozWx -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull kvm updates from Paolo Bonzini: "S390: - ultravisor communication device driver - fix TEID on terminating storage key ops RISC-V: - Added Sv57x4 support for G-stage page table - Added range based local HFENCE functions - Added remote HFENCE functions based on VCPU requests - Added ISA extension registers in ONE_REG interface - Updated KVM RISC-V maintainers entry to cover selftests support ARM: - Add support for the ARMv8.6 WFxT extension - Guard pages for the EL2 stacks - Trap and emulate AArch32 ID registers to hide unsupported features - Ability to select and save/restore the set of hypercalls exposed to the guest - Support for PSCI-initiated suspend in collaboration with userspace - GICv3 register-based LPI invalidation support - Move host PMU event merging into the vcpu data structure - GICv3 ITS save/restore fixes - The usual set of small-scale cleanups and fixes x86: - New ioctls to get/set TSC frequency for a whole VM - Allow userspace to opt out of hypercall patching - Only do MSR filtering for MSRs accessed by rdmsr/wrmsr AMD SEV improvements: - Add KVM_EXIT_SHUTDOWN metadata for SEV-ES - V_TSC_AUX support Nested virtualization improvements for AMD: - Support for "nested nested" optimizations (nested vVMLOAD/VMSAVE, nested vGIF) - Allow AVIC to co-exist with a nested guest running - Fixes for LBR virtualizations when a nested guest is running, and nested LBR virtualization support - PAUSE filtering for nested hypervisors Guest support: - Decoupling of vcpu_is_preempted from PV spinlocks" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (199 commits) KVM: x86: Fix the intel_pt PMI handling wrongly considered from guest KVM: selftests: x86: Sync the new name of the test case to .gitignore Documentation: kvm: reorder ARM-specific section about KVM_SYSTEM_EVENT_SUSPEND x86, kvm: use correct GFP flags for preemption disabled KVM: LAPIC: Drop pending LAPIC timer injection when canceling the timer x86/kvm: Alloc dummy async #PF token outside of raw spinlock KVM: x86: avoid calling x86 emulator without a decoded instruction KVM: SVM: Use kzalloc for sev ioctl interfaces to prevent kernel data leak x86/fpu: KVM: Set the base guest FPU uABI size to sizeof(struct kvm_xsave) s390/uv_uapi: depend on CONFIG_S390 KVM: selftests: x86: Fix test failure on arch lbr capable platforms KVM: LAPIC: Trace LAPIC timer expiration on every vmentry KVM: s390: selftest: Test suppression indication on key prot exception KVM: s390: Don't indicate suppression on dirtying, failing memop selftests: drivers/s390x: Add uvdevice tests drivers/s390/char: Add Ultravisor io device MAINTAINERS: Update KVM RISC-V entry to cover selftests support RISC-V: KVM: Introduce ISA extension register RISC-V: KVM: Cleanup stale TLB entries when host CPU changes RISC-V: KVM: Add remote HFENCE functions based on VCPU requests ...
621 lines
16 KiB
C
621 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Kernel-based Virtual Machine -- Performance Monitoring Unit support
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*
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* Copyright 2015 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Avi Kivity <avi@redhat.com>
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* Gleb Natapov <gleb@redhat.com>
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* Wei Huang <wei@redhat.com>
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*/
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <linux/bsearch.h>
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#include <linux/sort.h>
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#include <asm/perf_event.h>
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#include "x86.h"
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#include "cpuid.h"
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#include "lapic.h"
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#include "pmu.h"
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/* This is enough to filter the vast majority of currently defined events. */
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#define KVM_PMU_EVENT_FILTER_MAX_EVENTS 300
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/* NOTE:
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* - Each perf counter is defined as "struct kvm_pmc";
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* - There are two types of perf counters: general purpose (gp) and fixed.
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* gp counters are stored in gp_counters[] and fixed counters are stored
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* in fixed_counters[] respectively. Both of them are part of "struct
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* kvm_pmu";
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* - pmu.c understands the difference between gp counters and fixed counters.
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* However AMD doesn't support fixed-counters;
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* - There are three types of index to access perf counters (PMC):
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* 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
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* has MSR_K7_PERFCTRn.
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* 2. MSR Index (named idx): This normally is used by RDPMC instruction.
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* For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
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* C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
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* that it also supports fixed counters. idx can be used to as index to
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* gp and fixed counters.
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* 3. Global PMC Index (named pmc): pmc is an index specific to PMU
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* code. Each pmc, stored in kvm_pmc.idx field, is unique across
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* all perf counters (both gp and fixed). The mapping relationship
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* between pmc and perf counters is as the following:
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* * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
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* [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
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* * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
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*/
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static struct kvm_pmu_ops kvm_pmu_ops __read_mostly;
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#define KVM_X86_PMU_OP(func) \
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DEFINE_STATIC_CALL_NULL(kvm_x86_pmu_##func, \
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*(((struct kvm_pmu_ops *)0)->func));
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#define KVM_X86_PMU_OP_OPTIONAL KVM_X86_PMU_OP
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#include <asm/kvm-x86-pmu-ops.h>
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void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops)
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{
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memcpy(&kvm_pmu_ops, pmu_ops, sizeof(kvm_pmu_ops));
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#define __KVM_X86_PMU_OP(func) \
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static_call_update(kvm_x86_pmu_##func, kvm_pmu_ops.func);
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#define KVM_X86_PMU_OP(func) \
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WARN_ON(!kvm_pmu_ops.func); __KVM_X86_PMU_OP(func)
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#define KVM_X86_PMU_OP_OPTIONAL __KVM_X86_PMU_OP
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#include <asm/kvm-x86-pmu-ops.h>
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#undef __KVM_X86_PMU_OP
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}
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static inline bool pmc_is_enabled(struct kvm_pmc *pmc)
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{
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return static_call(kvm_x86_pmu_pmc_is_enabled)(pmc);
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}
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static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
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{
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struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
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struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
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kvm_pmu_deliver_pmi(vcpu);
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}
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static inline void __kvm_perf_overflow(struct kvm_pmc *pmc, bool in_pmi)
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{
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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/* Ignore counters that have been reprogrammed already. */
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if (test_and_set_bit(pmc->idx, pmu->reprogram_pmi))
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return;
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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if (!pmc->intr)
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return;
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/*
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* Inject PMI. If vcpu was in a guest mode during NMI PMI
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* can be ejected on a guest mode re-entry. Otherwise we can't
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* be sure that vcpu wasn't executing hlt instruction at the
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* time of vmexit and is not going to re-enter guest mode until
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* woken up. So we should wake it, but this is impossible from
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* NMI context. Do it from irq work instead.
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*/
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if (in_pmi && !kvm_handling_nmi_from_guest(pmc->vcpu))
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irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
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else
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kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
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}
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static void kvm_perf_overflow(struct perf_event *perf_event,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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__kvm_perf_overflow(pmc, true);
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}
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static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
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u64 config, bool exclude_user,
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bool exclude_kernel, bool intr)
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{
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struct perf_event *event;
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struct perf_event_attr attr = {
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.type = type,
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.size = sizeof(attr),
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.pinned = true,
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.exclude_idle = true,
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.exclude_host = 1,
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.exclude_user = exclude_user,
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.exclude_kernel = exclude_kernel,
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.config = config,
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};
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if (type == PERF_TYPE_HARDWARE && config >= PERF_COUNT_HW_MAX)
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return;
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attr.sample_period = get_sample_period(pmc, pmc->counter);
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if ((attr.config & HSW_IN_TX_CHECKPOINTED) &&
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guest_cpuid_is_intel(pmc->vcpu)) {
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/*
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* HSW_IN_TX_CHECKPOINTED is not supported with nonzero
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* period. Just clear the sample period so at least
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* allocating the counter doesn't fail.
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*/
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attr.sample_period = 0;
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}
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event = perf_event_create_kernel_counter(&attr, -1, current,
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kvm_perf_overflow, pmc);
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if (IS_ERR(event)) {
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pr_debug_ratelimited("kvm_pmu: event creation failed %ld for pmc->idx = %d\n",
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PTR_ERR(event), pmc->idx);
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return;
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}
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pmc->perf_event = event;
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pmc_to_pmu(pmc)->event_count++;
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clear_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi);
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pmc->is_paused = false;
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pmc->intr = intr;
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}
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static void pmc_pause_counter(struct kvm_pmc *pmc)
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{
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u64 counter = pmc->counter;
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if (!pmc->perf_event || pmc->is_paused)
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return;
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/* update counter, reset event value to avoid redundant accumulation */
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counter += perf_event_pause(pmc->perf_event, true);
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pmc->counter = counter & pmc_bitmask(pmc);
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pmc->is_paused = true;
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}
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static bool pmc_resume_counter(struct kvm_pmc *pmc)
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{
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if (!pmc->perf_event)
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return false;
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/* recalibrate sample period and check if it's accepted by perf core */
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if (perf_event_period(pmc->perf_event,
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get_sample_period(pmc, pmc->counter)))
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return false;
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/* reuse perf_event to serve as pmc_reprogram_counter() does*/
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perf_event_enable(pmc->perf_event);
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pmc->is_paused = false;
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clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi);
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return true;
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}
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static int cmp_u64(const void *pa, const void *pb)
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{
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u64 a = *(u64 *)pa;
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u64 b = *(u64 *)pb;
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return (a > b) - (a < b);
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}
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void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
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{
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u64 config;
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u32 type = PERF_TYPE_RAW;
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struct kvm *kvm = pmc->vcpu->kvm;
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struct kvm_pmu_event_filter *filter;
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struct kvm_pmu *pmu = vcpu_to_pmu(pmc->vcpu);
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bool allow_event = true;
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if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
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printk_once("kvm pmu: pin control bit is ignored\n");
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pmc->eventsel = eventsel;
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pmc_pause_counter(pmc);
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if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
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return;
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filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
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if (filter) {
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__u64 key = eventsel & AMD64_RAW_EVENT_MASK_NB;
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if (bsearch(&key, filter->events, filter->nevents,
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sizeof(__u64), cmp_u64))
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allow_event = filter->action == KVM_PMU_EVENT_ALLOW;
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else
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allow_event = filter->action == KVM_PMU_EVENT_DENY;
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}
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if (!allow_event)
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return;
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if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
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ARCH_PERFMON_EVENTSEL_INV |
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ARCH_PERFMON_EVENTSEL_CMASK |
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HSW_IN_TX |
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HSW_IN_TX_CHECKPOINTED))) {
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config = static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc);
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if (config != PERF_COUNT_HW_MAX)
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type = PERF_TYPE_HARDWARE;
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}
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if (type == PERF_TYPE_RAW)
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config = eventsel & pmu->raw_event_mask;
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if (pmc->current_config == eventsel && pmc_resume_counter(pmc))
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return;
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pmc_release_perf_event(pmc);
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pmc->current_config = eventsel;
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pmc_reprogram_counter(pmc, type, config,
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!(eventsel & ARCH_PERFMON_EVENTSEL_USR),
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!(eventsel & ARCH_PERFMON_EVENTSEL_OS),
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eventsel & ARCH_PERFMON_EVENTSEL_INT);
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}
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EXPORT_SYMBOL_GPL(reprogram_gp_counter);
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void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
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{
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unsigned en_field = ctrl & 0x3;
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bool pmi = ctrl & 0x8;
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struct kvm_pmu_event_filter *filter;
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struct kvm *kvm = pmc->vcpu->kvm;
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pmc_pause_counter(pmc);
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if (!en_field || !pmc_is_enabled(pmc))
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return;
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filter = srcu_dereference(kvm->arch.pmu_event_filter, &kvm->srcu);
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if (filter) {
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if (filter->action == KVM_PMU_EVENT_DENY &&
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test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
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return;
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if (filter->action == KVM_PMU_EVENT_ALLOW &&
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!test_bit(idx, (ulong *)&filter->fixed_counter_bitmap))
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return;
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}
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if (pmc->current_config == (u64)ctrl && pmc_resume_counter(pmc))
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return;
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pmc_release_perf_event(pmc);
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pmc->current_config = (u64)ctrl;
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pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
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static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc),
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!(en_field & 0x2), /* exclude user */
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!(en_field & 0x1), /* exclude kernel */
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pmi);
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}
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EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
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void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
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{
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struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, pmc_idx);
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if (!pmc)
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return;
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if (pmc_is_gp(pmc))
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reprogram_gp_counter(pmc, pmc->eventsel);
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else {
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int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
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u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
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reprogram_fixed_counter(pmc, ctrl, idx);
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}
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}
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EXPORT_SYMBOL_GPL(reprogram_counter);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int bit;
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for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) {
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struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, bit);
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if (unlikely(!pmc || !pmc->perf_event)) {
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clear_bit(bit, pmu->reprogram_pmi);
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continue;
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}
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reprogram_counter(pmu, bit);
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}
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/*
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* Unused perf_events are only released if the corresponding MSRs
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* weren't accessed during the last vCPU time slice. kvm_arch_sched_in
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* triggers KVM_REQ_PMU if cleanup is needed.
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*/
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if (unlikely(pmu->need_cleanup))
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kvm_pmu_cleanup(vcpu);
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}
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/* check if idx is a valid index to access PMU */
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bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx)
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{
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return static_call(kvm_x86_pmu_is_valid_rdpmc_ecx)(vcpu, idx);
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}
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bool is_vmware_backdoor_pmc(u32 pmc_idx)
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{
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switch (pmc_idx) {
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case VMWARE_BACKDOOR_PMC_HOST_TSC:
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case VMWARE_BACKDOOR_PMC_REAL_TIME:
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case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
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return true;
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}
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return false;
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}
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static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
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{
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u64 ctr_val;
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switch (idx) {
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case VMWARE_BACKDOOR_PMC_HOST_TSC:
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ctr_val = rdtsc();
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|
break;
|
|
case VMWARE_BACKDOOR_PMC_REAL_TIME:
|
|
ctr_val = ktime_get_boottime_ns();
|
|
break;
|
|
case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
|
|
ctr_val = ktime_get_boottime_ns() +
|
|
vcpu->kvm->arch.kvmclock_offset;
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
*data = ctr_val;
|
|
return 0;
|
|
}
|
|
|
|
int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
|
|
{
|
|
bool fast_mode = idx & (1u << 31);
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc;
|
|
u64 mask = fast_mode ? ~0u : ~0ull;
|
|
|
|
if (!pmu->version)
|
|
return 1;
|
|
|
|
if (is_vmware_backdoor_pmc(idx))
|
|
return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
|
|
|
|
pmc = static_call(kvm_x86_pmu_rdpmc_ecx_to_pmc)(vcpu, idx, &mask);
|
|
if (!pmc)
|
|
return 1;
|
|
|
|
if (!(kvm_read_cr4(vcpu) & X86_CR4_PCE) &&
|
|
(static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
|
|
(kvm_read_cr0(vcpu) & X86_CR0_PE))
|
|
return 1;
|
|
|
|
*data = pmc_read_counter(pmc) & mask;
|
|
return 0;
|
|
}
|
|
|
|
void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (lapic_in_kernel(vcpu)) {
|
|
static_call_cond(kvm_x86_pmu_deliver_pmi)(vcpu);
|
|
kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
|
|
}
|
|
}
|
|
|
|
bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
|
|
{
|
|
return static_call(kvm_x86_pmu_msr_idx_to_pmc)(vcpu, msr) ||
|
|
static_call(kvm_x86_pmu_is_valid_msr)(vcpu, msr);
|
|
}
|
|
|
|
static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc = static_call(kvm_x86_pmu_msr_idx_to_pmc)(vcpu, msr);
|
|
|
|
if (pmc)
|
|
__set_bit(pmc->idx, pmu->pmc_in_use);
|
|
}
|
|
|
|
int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|
{
|
|
return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info);
|
|
}
|
|
|
|
int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
|
{
|
|
kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index);
|
|
return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info);
|
|
}
|
|
|
|
/* refresh PMU settings. This function generally is called when underlying
|
|
* settings are changed (such as changes of PMU CPUID by guest VMs), which
|
|
* should rarely happen.
|
|
*/
|
|
void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
|
|
{
|
|
static_call(kvm_x86_pmu_refresh)(vcpu);
|
|
}
|
|
|
|
void kvm_pmu_reset(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
|
|
irq_work_sync(&pmu->irq_work);
|
|
static_call(kvm_x86_pmu_reset)(vcpu);
|
|
}
|
|
|
|
void kvm_pmu_init(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
|
|
memset(pmu, 0, sizeof(*pmu));
|
|
static_call(kvm_x86_pmu_init)(vcpu);
|
|
init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
|
|
pmu->event_count = 0;
|
|
pmu->need_cleanup = false;
|
|
kvm_pmu_refresh(vcpu);
|
|
}
|
|
|
|
static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
|
|
{
|
|
struct kvm_pmu *pmu = pmc_to_pmu(pmc);
|
|
|
|
if (pmc_is_fixed(pmc))
|
|
return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
|
|
pmc->idx - INTEL_PMC_IDX_FIXED) & 0x3;
|
|
|
|
return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
|
|
}
|
|
|
|
/* Release perf_events for vPMCs that have been unused for a full time slice. */
|
|
void kvm_pmu_cleanup(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc = NULL;
|
|
DECLARE_BITMAP(bitmask, X86_PMC_IDX_MAX);
|
|
int i;
|
|
|
|
pmu->need_cleanup = false;
|
|
|
|
bitmap_andnot(bitmask, pmu->all_valid_pmc_idx,
|
|
pmu->pmc_in_use, X86_PMC_IDX_MAX);
|
|
|
|
for_each_set_bit(i, bitmask, X86_PMC_IDX_MAX) {
|
|
pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, i);
|
|
|
|
if (pmc && pmc->perf_event && !pmc_speculative_in_use(pmc))
|
|
pmc_stop_counter(pmc);
|
|
}
|
|
|
|
static_call_cond(kvm_x86_pmu_cleanup)(vcpu);
|
|
|
|
bitmap_zero(pmu->pmc_in_use, X86_PMC_IDX_MAX);
|
|
}
|
|
|
|
void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
|
|
{
|
|
kvm_pmu_reset(vcpu);
|
|
}
|
|
|
|
static void kvm_pmu_incr_counter(struct kvm_pmc *pmc)
|
|
{
|
|
struct kvm_pmu *pmu = pmc_to_pmu(pmc);
|
|
u64 prev_count;
|
|
|
|
prev_count = pmc->counter;
|
|
pmc->counter = (pmc->counter + 1) & pmc_bitmask(pmc);
|
|
|
|
reprogram_counter(pmu, pmc->idx);
|
|
if (pmc->counter < prev_count)
|
|
__kvm_perf_overflow(pmc, false);
|
|
}
|
|
|
|
static inline bool eventsel_match_perf_hw_id(struct kvm_pmc *pmc,
|
|
unsigned int perf_hw_id)
|
|
{
|
|
u64 old_eventsel = pmc->eventsel;
|
|
unsigned int config;
|
|
|
|
pmc->eventsel &= (ARCH_PERFMON_EVENTSEL_EVENT | ARCH_PERFMON_EVENTSEL_UMASK);
|
|
config = static_call(kvm_x86_pmu_pmc_perf_hw_id)(pmc);
|
|
pmc->eventsel = old_eventsel;
|
|
return config == perf_hw_id;
|
|
}
|
|
|
|
static inline bool cpl_is_matched(struct kvm_pmc *pmc)
|
|
{
|
|
bool select_os, select_user;
|
|
u64 config = pmc->current_config;
|
|
|
|
if (pmc_is_gp(pmc)) {
|
|
select_os = config & ARCH_PERFMON_EVENTSEL_OS;
|
|
select_user = config & ARCH_PERFMON_EVENTSEL_USR;
|
|
} else {
|
|
select_os = config & 0x1;
|
|
select_user = config & 0x2;
|
|
}
|
|
|
|
return (static_call(kvm_x86_get_cpl)(pmc->vcpu) == 0) ? select_os : select_user;
|
|
}
|
|
|
|
void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 perf_hw_id)
|
|
{
|
|
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
|
struct kvm_pmc *pmc;
|
|
int i;
|
|
|
|
for_each_set_bit(i, pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX) {
|
|
pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, i);
|
|
|
|
if (!pmc || !pmc_is_enabled(pmc) || !pmc_speculative_in_use(pmc))
|
|
continue;
|
|
|
|
/* Ignore checks for edge detect, pin control, invert and CMASK bits */
|
|
if (eventsel_match_perf_hw_id(pmc, perf_hw_id) && cpl_is_matched(pmc))
|
|
kvm_pmu_incr_counter(pmc);
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_pmu_trigger_event);
|
|
|
|
int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp)
|
|
{
|
|
struct kvm_pmu_event_filter tmp, *filter;
|
|
size_t size;
|
|
int r;
|
|
|
|
if (copy_from_user(&tmp, argp, sizeof(tmp)))
|
|
return -EFAULT;
|
|
|
|
if (tmp.action != KVM_PMU_EVENT_ALLOW &&
|
|
tmp.action != KVM_PMU_EVENT_DENY)
|
|
return -EINVAL;
|
|
|
|
if (tmp.flags != 0)
|
|
return -EINVAL;
|
|
|
|
if (tmp.nevents > KVM_PMU_EVENT_FILTER_MAX_EVENTS)
|
|
return -E2BIG;
|
|
|
|
size = struct_size(filter, events, tmp.nevents);
|
|
filter = kmalloc(size, GFP_KERNEL_ACCOUNT);
|
|
if (!filter)
|
|
return -ENOMEM;
|
|
|
|
r = -EFAULT;
|
|
if (copy_from_user(filter, argp, size))
|
|
goto cleanup;
|
|
|
|
/* Ensure nevents can't be changed between the user copies. */
|
|
*filter = tmp;
|
|
|
|
/*
|
|
* Sort the in-kernel list so that we can search it with bsearch.
|
|
*/
|
|
sort(&filter->events, filter->nevents, sizeof(__u64), cmp_u64, NULL);
|
|
|
|
mutex_lock(&kvm->lock);
|
|
filter = rcu_replace_pointer(kvm->arch.pmu_event_filter, filter,
|
|
mutex_is_locked(&kvm->lock));
|
|
mutex_unlock(&kvm->lock);
|
|
|
|
synchronize_srcu_expedited(&kvm->srcu);
|
|
r = 0;
|
|
cleanup:
|
|
kfree(filter);
|
|
return r;
|
|
}
|