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![Hans de Goede](/assets/img/avatar_default.png)
This reverts commit4c5e242d3e
. Prior to4c5e242d3e
("x86/PCI: Clip only host bridge windows for E820 regions"), E820 regions did not affect PCI host bridge windows. We only looked at E820 regions and avoided them when allocating new MMIO space. If firmware PCI bridge window and BAR assignments used E820 regions, we left them alone. After4c5e242d3e
, we removed E820 regions from the PCI host bridge windows before looking at BARs, so firmware assignments in E820 regions looked like errors, and we moved things around to fit in the space left (if any) after removing the E820 regions. This unnecessary BAR reassignment broke several machines. Guilherme reported that Steam Deck fails to boot after4c5e242d3e
. We clipped the window that contained most 32-bit BARs: BIOS-e820: [mem 0x00000000a0000000-0x00000000a00fffff] reserved acpi PNP0A08:00: clipped [mem 0x80000000-0xf7ffffff window] to [mem 0xa0100000-0xf7ffffff window] for e820 entry [mem 0xa0000000-0xa00fffff] which forced us to reassign all those BARs, for example, this NVMe BAR: pci 0000:00:01.2: PCI bridge to [bus 01] pci 0000:00:01.2: bridge window [mem 0x80600000-0x806fffff] pci 0000:01:00.0: BAR 0: [mem 0x80600000-0x80603fff 64bit] pci 0000:00:01.2: can't claim window [mem 0x80600000-0x806fffff]: no compatible bridge window pci 0000:01:00.0: can't claim BAR 0 [mem 0x80600000-0x80603fff 64bit]: no compatible bridge window pci 0000:00:01.2: bridge window: assigned [mem 0xa0100000-0xa01fffff] pci 0000:01:00.0: BAR 0: assigned [mem 0xa0100000-0xa0103fff 64bit] All the reassignments were successful, so the devices should have been functional at the new addresses, but some were not. Andy reported a similar failure on an Intel MID platform. Benjamin reported a similar failure on a VMWare Fusion VM. Note: this is not a clean revert; this revert keeps the later change to make the clipping dependent on a new pci_use_e820 bool, moving the checking of this bool to arch_remove_reservations(). [bhelgaas: commit log, add more reporters and testers] BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=216109 Reported-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reported-by: Benjamin Coddington <bcodding@redhat.com> Reported-by: Jongman Heo <jongman.heo@gmail.com> Fixes:4c5e242d3e
("x86/PCI: Clip only host bridge windows for E820 regions") Link: https://lore.kernel.org/r/20220612144325.85366-1-hdegoede@redhat.com Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Benjamin Coddington <bcodding@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
512 lines
14 KiB
C
512 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <linux/pci-acpi.h>
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#include <asm/numa.h>
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#include <asm/pci_x86.h>
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struct pci_root_info {
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struct acpi_pci_root_info common;
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struct pci_sysdata sd;
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#ifdef CONFIG_PCI_MMCONFIG
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bool mcfg_added;
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u8 start_bus;
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u8 end_bus;
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#endif
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};
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bool pci_use_e820 = true;
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static bool pci_use_crs = true;
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static bool pci_ignore_seg;
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static int __init set_use_crs(const struct dmi_system_id *id)
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{
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pci_use_crs = true;
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return 0;
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}
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static int __init set_nouse_crs(const struct dmi_system_id *id)
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{
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pci_use_crs = false;
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return 0;
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}
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static int __init set_ignore_seg(const struct dmi_system_id *id)
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{
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printk(KERN_INFO "PCI: %s detected: ignoring ACPI _SEG\n", id->ident);
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pci_ignore_seg = true;
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return 0;
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}
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static int __init set_no_e820(const struct dmi_system_id *id)
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{
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printk(KERN_INFO "PCI: %s detected: not clipping E820 regions from _CRS\n",
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id->ident);
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pci_use_e820 = false;
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return 0;
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}
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static const struct dmi_system_id pci_crs_quirks[] __initconst = {
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/* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */
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{
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.callback = set_use_crs,
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.ident = "IBM System x3800",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
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DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=16007 */
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/* 2006 AMD HT/VIA system with two host bridges */
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{
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.callback = set_use_crs,
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.ident = "ASRock ALiveSATA2-GLAN",
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.matches = {
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DMI_MATCH(DMI_PRODUCT_NAME, "ALiveSATA2-GLAN"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=30552 */
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/* 2006 AMD HT/VIA system with two host bridges */
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{
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.callback = set_use_crs,
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.ident = "ASUS M2V-MX SE",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
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DMI_MATCH(DMI_BOARD_NAME, "M2V-MX SE"),
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DMI_MATCH(DMI_BIOS_VENDOR, "American Megatrends Inc."),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=42619 */
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{
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.callback = set_use_crs,
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.ident = "MSI MS-7253",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
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DMI_MATCH(DMI_BOARD_NAME, "MS-7253"),
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DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
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},
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},
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/* https://bugs.launchpad.net/ubuntu/+source/alsa-driver/+bug/931368 */
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/* https://bugs.launchpad.net/ubuntu/+source/alsa-driver/+bug/1033299 */
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{
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.callback = set_use_crs,
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.ident = "Foxconn K8M890-8237A",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Foxconn"),
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DMI_MATCH(DMI_BOARD_NAME, "K8M890-8237A"),
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DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
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},
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},
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/* Now for the blacklist.. */
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/* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
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{
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.callback = set_nouse_crs,
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.ident = "Dell Studio 1557",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Studio 1557"),
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DMI_MATCH(DMI_BIOS_VERSION, "A09"),
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},
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},
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/* https://bugzilla.redhat.com/show_bug.cgi?id=769657 */
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{
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.callback = set_nouse_crs,
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.ident = "Thinkpad SL510",
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.matches = {
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DMI_MATCH(DMI_BOARD_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_BOARD_NAME, "2847DFG"),
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DMI_MATCH(DMI_BIOS_VERSION, "6JET85WW (1.43 )"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=42606 */
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{
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.callback = set_nouse_crs,
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.ident = "Supermicro X8DTH",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
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DMI_MATCH(DMI_PRODUCT_NAME, "X8DTH-i/6/iF/6F"),
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DMI_MATCH(DMI_BIOS_VERSION, "2.0a"),
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},
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},
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/* https://bugzilla.kernel.org/show_bug.cgi?id=15362 */
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{
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.callback = set_ignore_seg,
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.ident = "HP xw9300",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
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DMI_MATCH(DMI_PRODUCT_NAME, "HP xw9300 Workstation"),
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},
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},
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/*
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* Many Lenovo models with "IIL" in their DMI_PRODUCT_VERSION have
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* an E820 reserved region that covers the entire 32-bit host
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* bridge memory window from _CRS. Using the E820 region to clip
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* _CRS means no space is available for hot-added or uninitialized
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* PCI devices. This typically breaks I2C controllers for touchpads
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* and hot-added Thunderbolt devices. See the commit log for
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* models known to require this quirk and related bug reports.
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*/
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{
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.callback = set_no_e820,
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.ident = "Lenovo *IIL* product version",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "IIL"),
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},
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},
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/*
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* The Acer Spin 5 (SP513-54N) has the same E820 reservation covering
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* the entire _CRS 32-bit window issue as the Lenovo *IIL* models.
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* See https://bugs.launchpad.net/bugs/1884232
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*/
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{
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.callback = set_no_e820,
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.ident = "Acer Spin 5 (SP513-54N)",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Spin SP513-54N"),
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},
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},
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/*
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* Clevo X170KM-G barebones have the same E820 reservation covering
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* the entire _CRS 32-bit window issue as the Lenovo *IIL* models.
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* See https://bugzilla.kernel.org/show_bug.cgi?id=214259
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*/
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{
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.callback = set_no_e820,
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.ident = "Clevo X170KM-G Barebone",
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.matches = {
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DMI_MATCH(DMI_BOARD_NAME, "X170KM-G"),
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},
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},
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{}
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};
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void __init pci_acpi_crs_quirks(void)
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{
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int year = dmi_get_bios_year();
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if (year >= 0 && year < 2008 && iomem_resource.end <= 0xffffffff)
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pci_use_crs = false;
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/*
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* Some firmware includes unusable space (host bridge registers,
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* hidden PCI device BARs, etc) in PCI host bridge _CRS. This is a
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* firmware defect, and 4dc2287c1805 ("x86: avoid E820 regions when
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* allocating address space") has clipped out the unusable space in
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* the past.
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*
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* But other firmware supplies E820 reserved regions that cover
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* entire _CRS windows, so clipping throws away the entire window,
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* leaving none for hot-added or uninitialized devices. These E820
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* entries are probably *not* a firmware defect, so disable the
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* clipping by default for post-2022 machines.
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*
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* We already have quirks to disable clipping for pre-2023
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* machines, and we'll likely need quirks to *enable* clipping for
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* post-2022 machines that incorrectly include unusable space in
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* _CRS.
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*/
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if (year >= 2023)
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pci_use_e820 = false;
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dmi_check_system(pci_crs_quirks);
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/*
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* If the user specifies "pci=use_crs" or "pci=nocrs" explicitly, that
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* takes precedence over anything we figured out above.
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*/
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if (pci_probe & PCI_ROOT_NO_CRS)
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pci_use_crs = false;
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else if (pci_probe & PCI_USE__CRS)
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pci_use_crs = true;
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printk(KERN_INFO "PCI: %s host bridge windows from ACPI; "
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"if necessary, use \"pci=%s\" and report a bug\n",
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pci_use_crs ? "Using" : "Ignoring",
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pci_use_crs ? "nocrs" : "use_crs");
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/* "pci=use_e820"/"pci=no_e820" on the kernel cmdline takes precedence */
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if (pci_probe & PCI_NO_E820)
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pci_use_e820 = false;
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else if (pci_probe & PCI_USE_E820)
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pci_use_e820 = true;
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printk(KERN_INFO "PCI: %s E820 reservations for host bridge windows\n",
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pci_use_e820 ? "Using" : "Ignoring");
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if (pci_probe & (PCI_NO_E820 | PCI_USE_E820))
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printk(KERN_INFO "PCI: Please notify linux-pci@vger.kernel.org so future kernels can this automatically\n");
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}
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#ifdef CONFIG_PCI_MMCONFIG
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static int check_segment(u16 seg, struct device *dev, char *estr)
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{
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if (seg) {
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dev_err(dev,
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"%s can't access PCI configuration "
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"space under this host bridge.\n",
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estr);
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return -EIO;
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}
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/*
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* Failure in adding MMCFG information is not fatal,
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* just can't access extended configuration space of
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* devices under this host bridge.
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*/
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dev_warn(dev,
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"%s can't access extended PCI configuration "
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"space under this bridge.\n",
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estr);
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return 0;
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}
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static int setup_mcfg_map(struct acpi_pci_root_info *ci)
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{
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int result, seg;
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struct pci_root_info *info;
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struct acpi_pci_root *root = ci->root;
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struct device *dev = &ci->bridge->dev;
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info = container_of(ci, struct pci_root_info, common);
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info->start_bus = (u8)root->secondary.start;
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info->end_bus = (u8)root->secondary.end;
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info->mcfg_added = false;
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seg = info->sd.domain;
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/* return success if MMCFG is not in use */
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if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
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return 0;
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if (!(pci_probe & PCI_PROBE_MMCONF))
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return check_segment(seg, dev, "MMCONFIG is disabled,");
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result = pci_mmconfig_insert(dev, seg, info->start_bus, info->end_bus,
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root->mcfg_addr);
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if (result == 0) {
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/* enable MMCFG if it hasn't been enabled yet */
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if (raw_pci_ext_ops == NULL)
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raw_pci_ext_ops = &pci_mmcfg;
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info->mcfg_added = true;
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} else if (result != -EEXIST)
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return check_segment(seg, dev,
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"fail to add MMCONFIG information,");
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return 0;
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}
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static void teardown_mcfg_map(struct acpi_pci_root_info *ci)
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{
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struct pci_root_info *info;
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info = container_of(ci, struct pci_root_info, common);
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if (info->mcfg_added) {
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pci_mmconfig_delete(info->sd.domain,
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info->start_bus, info->end_bus);
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info->mcfg_added = false;
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}
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}
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#else
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static int setup_mcfg_map(struct acpi_pci_root_info *ci)
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{
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return 0;
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}
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static void teardown_mcfg_map(struct acpi_pci_root_info *ci)
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{
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}
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#endif
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static int pci_acpi_root_get_node(struct acpi_pci_root *root)
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{
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int busnum = root->secondary.start;
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struct acpi_device *device = root->device;
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int node = acpi_get_node(device->handle);
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if (node == NUMA_NO_NODE) {
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node = x86_pci_root_bus_node(busnum);
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if (node != 0 && node != NUMA_NO_NODE)
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dev_info(&device->dev, FW_BUG "no _PXM; falling back to node %d from hardware (may be inconsistent with ACPI node numbers)\n",
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node);
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}
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if (node != NUMA_NO_NODE && !node_online(node))
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node = NUMA_NO_NODE;
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return node;
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}
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static int pci_acpi_root_init_info(struct acpi_pci_root_info *ci)
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{
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return setup_mcfg_map(ci);
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}
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static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
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{
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teardown_mcfg_map(ci);
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kfree(container_of(ci, struct pci_root_info, common));
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}
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/*
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* An IO port or MMIO resource assigned to a PCI host bridge may be
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* consumed by the host bridge itself or available to its child
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* bus/devices. The ACPI specification defines a bit (Producer/Consumer)
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* to tell whether the resource is consumed by the host bridge itself,
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* but firmware hasn't used that bit consistently, so we can't rely on it.
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*
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* On x86 and IA64 platforms, all IO port and MMIO resources are assumed
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* to be available to child bus/devices except one special case:
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* IO port [0xCF8-0xCFF] is consumed by the host bridge itself
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* to access PCI configuration space.
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*
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* So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
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*/
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static bool resource_is_pcicfg_ioport(struct resource *res)
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{
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return (res->flags & IORESOURCE_IO) &&
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res->start == 0xCF8 && res->end == 0xCFF;
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}
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static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
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{
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struct acpi_device *device = ci->bridge;
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int busnum = ci->root->secondary.start;
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struct resource_entry *entry, *tmp;
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int status;
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status = acpi_pci_probe_root_resources(ci);
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if (pci_use_crs) {
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resource_list_for_each_entry_safe(entry, tmp, &ci->resources)
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if (resource_is_pcicfg_ioport(entry->res))
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resource_list_destroy_entry(entry);
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return status;
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}
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resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
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dev_printk(KERN_DEBUG, &device->dev,
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"host bridge window %pR (ignored)\n", entry->res);
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resource_list_destroy_entry(entry);
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}
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x86_pci_root_bus_resources(busnum, &ci->resources);
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return 0;
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}
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static struct acpi_pci_root_ops acpi_pci_root_ops = {
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.pci_ops = &pci_root_ops,
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.init_info = pci_acpi_root_init_info,
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.release_info = pci_acpi_root_release_info,
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.prepare_resources = pci_acpi_root_prepare_resources,
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};
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struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
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{
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int domain = root->segment;
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int busnum = root->secondary.start;
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int node = pci_acpi_root_get_node(root);
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struct pci_bus *bus;
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if (pci_ignore_seg)
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root->segment = domain = 0;
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if (domain && !pci_domains_supported) {
|
|
printk(KERN_WARNING "pci_bus %04x:%02x: "
|
|
"ignored (multiple domains not supported)\n",
|
|
domain, busnum);
|
|
return NULL;
|
|
}
|
|
|
|
bus = pci_find_bus(domain, busnum);
|
|
if (bus) {
|
|
/*
|
|
* If the desired bus has been scanned already, replace
|
|
* its bus->sysdata.
|
|
*/
|
|
struct pci_sysdata sd = {
|
|
.domain = domain,
|
|
.node = node,
|
|
.companion = root->device
|
|
};
|
|
|
|
memcpy(bus->sysdata, &sd, sizeof(sd));
|
|
} else {
|
|
struct pci_root_info *info;
|
|
|
|
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
|
if (!info)
|
|
dev_err(&root->device->dev,
|
|
"pci_bus %04x:%02x: ignored (out of memory)\n",
|
|
domain, busnum);
|
|
else {
|
|
info->sd.domain = domain;
|
|
info->sd.node = node;
|
|
info->sd.companion = root->device;
|
|
bus = acpi_pci_root_create(root, &acpi_pci_root_ops,
|
|
&info->common, &info->sd);
|
|
}
|
|
}
|
|
|
|
/* After the PCI-E bus has been walked and all devices discovered,
|
|
* configure any settings of the fabric that might be necessary.
|
|
*/
|
|
if (bus) {
|
|
struct pci_bus *child;
|
|
list_for_each_entry(child, &bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
}
|
|
|
|
return bus;
|
|
}
|
|
|
|
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
|
|
{
|
|
/*
|
|
* We pass NULL as parent to pci_create_root_bus(), so if it is not NULL
|
|
* here, pci_create_root_bus() has been called by someone else and
|
|
* sysdata is likely to be different from what we expect. Let it go in
|
|
* that case.
|
|
*/
|
|
if (!bridge->dev.parent) {
|
|
struct pci_sysdata *sd = bridge->bus->sysdata;
|
|
ACPI_COMPANION_SET(&bridge->dev, sd->companion);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int __init pci_acpi_init(void)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
|
|
if (acpi_noirq)
|
|
return -ENODEV;
|
|
|
|
printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
|
|
acpi_irq_penalty_init();
|
|
pcibios_enable_irq = acpi_pci_irq_enable;
|
|
pcibios_disable_irq = acpi_pci_irq_disable;
|
|
x86_init.pci.init_irq = x86_init_noop;
|
|
|
|
if (pci_routeirq) {
|
|
/*
|
|
* PCI IRQ routing is set up by pci_enable_device(), but we
|
|
* also do it here in case there are still broken drivers that
|
|
* don't use pci_enable_device().
|
|
*/
|
|
printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
|
|
for_each_pci_dev(dev)
|
|
acpi_pci_irq_enable(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|