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![Yang Li](/assets/img/avatar_default.png)
Return boolean values ("true" or "false") instead of 1 or 0 from bool functions. This fixes the following warnings from coccicheck: ./arch/x86/pci/mmconfig-shared.c:464:9-10: WARNING: return of 0/1 in function 'is_mmconf_reserved' with return type bool ./arch/x86/pci/mmconfig-shared.c:493:5-6: WARNING: return of 0/1 in function 'is_mmconf_reserved' with return type bool ./arch/x86/pci/mmconfig-shared.c:501:9-10: WARNING: return of 0/1 in function 'is_mmconf_reserved' with return type bool ./arch/x86/pci/mmconfig-shared.c:522:5-6: WARNING: return of 0/1 in function 'is_mmconf_reserved' with return type bool Link: https://lore.kernel.org/r/1615794000-102771-1-git-send-email-yang.lee@linux.alibaba.com Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
815 lines
19 KiB
C
815 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mmconfig-shared.c - Low-level direct PCI config space access via
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* MMCONFIG - common code between i386 and x86-64.
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*
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* This code does:
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* - known chipset handling
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* - ACPI decoding and validation
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*
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* Per-architecture code takes care of the mappings and accesses
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* themselves.
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*/
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitmap.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/rculist.h>
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#include <asm/e820/api.h>
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#include <asm/pci_x86.h>
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#include <asm/acpi.h>
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#define PREFIX "PCI: "
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/* Indicate if the mmcfg resources have been placed into the resource table. */
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static bool pci_mmcfg_running_state;
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static bool pci_mmcfg_arch_init_failed;
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static DEFINE_MUTEX(pci_mmcfg_lock);
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#define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map)
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LIST_HEAD(pci_mmcfg_list);
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static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
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{
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if (cfg->res.parent)
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release_resource(&cfg->res);
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list_del(&cfg->list);
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kfree(cfg);
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}
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static void __init free_all_mmcfg(void)
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{
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struct pci_mmcfg_region *cfg, *tmp;
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pci_mmcfg_arch_free();
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list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
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pci_mmconfig_remove(cfg);
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}
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static void list_add_sorted(struct pci_mmcfg_region *new)
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{
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struct pci_mmcfg_region *cfg;
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/* keep list sorted by segment and starting bus number */
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list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) {
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if (cfg->segment > new->segment ||
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(cfg->segment == new->segment &&
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cfg->start_bus >= new->start_bus)) {
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list_add_tail_rcu(&new->list, &cfg->list);
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return;
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}
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}
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list_add_tail_rcu(&new->list, &pci_mmcfg_list);
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}
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static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
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int end, u64 addr)
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{
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struct pci_mmcfg_region *new;
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struct resource *res;
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if (addr == 0)
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return NULL;
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new = kzalloc(sizeof(*new), GFP_KERNEL);
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if (!new)
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return NULL;
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new->address = addr;
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new->segment = segment;
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new->start_bus = start;
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new->end_bus = end;
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res = &new->res;
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res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
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res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
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res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
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"PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
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res->name = new->name;
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return new;
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}
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struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
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int end, u64 addr)
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{
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struct pci_mmcfg_region *new;
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new = pci_mmconfig_alloc(segment, start, end, addr);
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if (new) {
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mutex_lock(&pci_mmcfg_lock);
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list_add_sorted(new);
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mutex_unlock(&pci_mmcfg_lock);
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pr_info(PREFIX
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"MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
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"(base %#lx)\n",
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segment, start, end, &new->res, (unsigned long)addr);
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}
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return new;
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}
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struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
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{
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struct pci_mmcfg_region *cfg;
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list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held())
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if (cfg->segment == segment &&
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cfg->start_bus <= bus && bus <= cfg->end_bus)
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return cfg;
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return NULL;
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}
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static const char *__init pci_mmcfg_e7520(void)
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{
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u32 win;
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raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
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win = win & 0xf000;
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if (win == 0x0000 || win == 0xf000)
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return NULL;
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if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
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return NULL;
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return "Intel Corporation E7520 Memory Controller Hub";
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}
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static const char *__init pci_mmcfg_intel_945(void)
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{
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u32 pciexbar, mask = 0, len = 0;
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raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
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/* Enable bit */
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if (!(pciexbar & 1))
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return NULL;
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/* Size bits */
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switch ((pciexbar >> 1) & 3) {
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case 0:
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mask = 0xf0000000U;
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len = 0x10000000U;
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break;
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case 1:
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mask = 0xf8000000U;
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len = 0x08000000U;
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break;
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case 2:
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mask = 0xfc000000U;
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len = 0x04000000U;
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break;
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default:
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return NULL;
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}
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/* Errata #2, things break when not aligned on a 256Mb boundary */
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/* Can only happen in 64M/128M mode */
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if ((pciexbar & mask) & 0x0fffffffU)
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return NULL;
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/* Don't hit the APIC registers and their friends */
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if ((pciexbar & mask) >= 0xf0000000U)
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return NULL;
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if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
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return NULL;
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return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
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}
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static const char *__init pci_mmcfg_amd_fam10h(void)
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{
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u32 low, high, address;
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u64 base, msr;
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int i;
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unsigned segnbits = 0, busnbits, end_bus;
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if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
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return NULL;
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address = MSR_FAM10H_MMIO_CONF_BASE;
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if (rdmsr_safe(address, &low, &high))
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return NULL;
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msr = high;
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msr <<= 32;
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msr |= low;
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/* mmconfig is not enable */
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if (!(msr & FAM10H_MMIO_CONF_ENABLE))
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return NULL;
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base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
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busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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FAM10H_MMIO_CONF_BUSRANGE_MASK;
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/*
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* only handle bus 0 ?
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* need to skip it
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*/
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if (!busnbits)
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return NULL;
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if (busnbits > 8) {
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segnbits = busnbits - 8;
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busnbits = 8;
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}
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end_bus = (1 << busnbits) - 1;
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for (i = 0; i < (1 << segnbits); i++)
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if (pci_mmconfig_add(i, 0, end_bus,
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base + (1<<28) * i) == NULL) {
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free_all_mmcfg();
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return NULL;
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}
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return "AMD Family 10h NB";
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}
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static bool __initdata mcp55_checked;
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static const char *__init pci_mmcfg_nvidia_mcp55(void)
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{
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int bus;
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int mcp55_mmconf_found = 0;
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static const u32 extcfg_regnum __initconst = 0x90;
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static const u32 extcfg_regsize __initconst = 4;
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static const u32 extcfg_enable_mask __initconst = 1 << 31;
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static const u32 extcfg_start_mask __initconst = 0xff << 16;
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static const int extcfg_start_shift __initconst = 16;
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static const u32 extcfg_size_mask __initconst = 0x3 << 28;
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static const int extcfg_size_shift __initconst = 28;
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static const int extcfg_sizebus[] __initconst = {
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0x100, 0x80, 0x40, 0x20
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};
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static const u32 extcfg_base_mask[] __initconst = {
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0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
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};
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static const int extcfg_base_lshift __initconst = 25;
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/*
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* do check if amd fam10h already took over
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*/
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if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
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return NULL;
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mcp55_checked = true;
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for (bus = 0; bus < 256; bus++) {
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u64 base;
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u32 l, extcfg;
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u16 vendor, device;
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int start, size_index, end;
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raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
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vendor = l & 0xffff;
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device = (l >> 16) & 0xffff;
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if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
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continue;
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raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
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extcfg_regsize, &extcfg);
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if (!(extcfg & extcfg_enable_mask))
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continue;
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size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
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base = extcfg & extcfg_base_mask[size_index];
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/* base could > 4G */
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base <<= extcfg_base_lshift;
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start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
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end = start + extcfg_sizebus[size_index] - 1;
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if (pci_mmconfig_add(0, start, end, base) == NULL)
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continue;
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mcp55_mmconf_found++;
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}
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if (!mcp55_mmconf_found)
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return NULL;
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return "nVidia MCP55";
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}
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struct pci_mmcfg_hostbridge_probe {
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u32 bus;
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u32 devfn;
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u32 vendor;
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u32 device;
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const char *(*probe)(void);
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};
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static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
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{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
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{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
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{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
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0x1200, pci_mmcfg_amd_fam10h },
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{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
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0x1200, pci_mmcfg_amd_fam10h },
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{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
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0x0369, pci_mmcfg_nvidia_mcp55 },
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};
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static void __init pci_mmcfg_check_end_bus_number(void)
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{
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struct pci_mmcfg_region *cfg, *cfgx;
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/* Fixup overlaps */
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list_for_each_entry(cfg, &pci_mmcfg_list, list) {
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if (cfg->end_bus < cfg->start_bus)
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cfg->end_bus = 255;
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/* Don't access the list head ! */
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if (cfg->list.next == &pci_mmcfg_list)
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break;
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cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
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if (cfg->end_bus >= cfgx->start_bus)
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cfg->end_bus = cfgx->start_bus - 1;
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}
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}
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static int __init pci_mmcfg_check_hostbridge(void)
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{
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u32 l;
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u32 bus, devfn;
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u16 vendor, device;
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int i;
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const char *name;
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if (!raw_pci_ops)
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return 0;
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free_all_mmcfg();
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for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
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bus = pci_mmcfg_probes[i].bus;
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devfn = pci_mmcfg_probes[i].devfn;
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raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
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vendor = l & 0xffff;
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device = (l >> 16) & 0xffff;
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name = NULL;
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if (pci_mmcfg_probes[i].vendor == vendor &&
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pci_mmcfg_probes[i].device == device)
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name = pci_mmcfg_probes[i].probe();
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if (name)
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pr_info(PREFIX "%s with MMCONFIG support\n", name);
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}
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/* some end_bus_number is crazy, fix it */
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pci_mmcfg_check_end_bus_number();
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return !list_empty(&pci_mmcfg_list);
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}
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static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
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{
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struct resource *mcfg_res = data;
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struct acpi_resource_address64 address;
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acpi_status status;
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if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
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struct acpi_resource_fixed_memory32 *fixmem32 =
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&res->data.fixed_memory32;
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if (!fixmem32)
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return AE_OK;
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if ((mcfg_res->start >= fixmem32->address) &&
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(mcfg_res->end < (fixmem32->address +
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fixmem32->address_length))) {
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mcfg_res->flags = 1;
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return AE_CTRL_TERMINATE;
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}
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}
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if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
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(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
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return AE_OK;
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status = acpi_resource_to_address64(res, &address);
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if (ACPI_FAILURE(status) ||
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(address.address.address_length <= 0) ||
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(address.resource_type != ACPI_MEMORY_RANGE))
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return AE_OK;
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if ((mcfg_res->start >= address.address.minimum) &&
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(mcfg_res->end < (address.address.minimum + address.address.address_length))) {
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mcfg_res->flags = 1;
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return AE_CTRL_TERMINATE;
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}
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return AE_OK;
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}
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static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
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void *context, void **rv)
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{
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struct resource *mcfg_res = context;
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acpi_walk_resources(handle, METHOD_NAME__CRS,
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check_mcfg_resource, context);
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if (mcfg_res->flags)
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return AE_CTRL_TERMINATE;
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return AE_OK;
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}
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static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used)
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{
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struct resource mcfg_res;
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mcfg_res.start = start;
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mcfg_res.end = end - 1;
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mcfg_res.flags = 0;
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acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
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if (!mcfg_res.flags)
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acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
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NULL);
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return mcfg_res.flags;
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}
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typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type);
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static bool __ref is_mmconf_reserved(check_reserved_t is_reserved,
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struct pci_mmcfg_region *cfg,
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struct device *dev, int with_e820)
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{
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u64 addr = cfg->res.start;
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u64 size = resource_size(&cfg->res);
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u64 old_size = size;
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int num_buses;
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char *method = with_e820 ? "E820" : "ACPI motherboard resources";
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while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) {
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size >>= 1;
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if (size < (16UL<<20))
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break;
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}
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if (size < (16UL<<20) && size != old_size)
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return false;
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if (dev)
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dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
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&cfg->res, method);
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else
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pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
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&cfg->res, method);
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if (old_size != size) {
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/* update end_bus */
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cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
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num_buses = cfg->end_bus - cfg->start_bus + 1;
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cfg->res.end = cfg->res.start +
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PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
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snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
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"PCI MMCONFIG %04x [bus %02x-%02x]",
|
|
cfg->segment, cfg->start_bus, cfg->end_bus);
|
|
|
|
if (dev)
|
|
dev_info(dev,
|
|
"MMCONFIG "
|
|
"at %pR (base %#lx) (size reduced!)\n",
|
|
&cfg->res, (unsigned long) cfg->address);
|
|
else
|
|
pr_info(PREFIX
|
|
"MMCONFIG for %04x [bus%02x-%02x] "
|
|
"at %pR (base %#lx) (size reduced!)\n",
|
|
cfg->segment, cfg->start_bus, cfg->end_bus,
|
|
&cfg->res, (unsigned long) cfg->address);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool __ref
|
|
pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int early)
|
|
{
|
|
if (!early && !acpi_disabled) {
|
|
if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
|
|
return true;
|
|
|
|
if (dev)
|
|
dev_info(dev, FW_INFO
|
|
"MMCONFIG at %pR not reserved in "
|
|
"ACPI motherboard resources\n",
|
|
&cfg->res);
|
|
else
|
|
pr_info(FW_INFO PREFIX
|
|
"MMCONFIG at %pR not reserved in "
|
|
"ACPI motherboard resources\n",
|
|
&cfg->res);
|
|
}
|
|
|
|
/*
|
|
* e820__mapped_all() is marked as __init.
|
|
* All entries from ACPI MCFG table have been checked at boot time.
|
|
* For MCFG information constructed from hotpluggable host bridge's
|
|
* _CBA method, just assume it's reserved.
|
|
*/
|
|
if (pci_mmcfg_running_state)
|
|
return true;
|
|
|
|
/* Don't try to do this check unless configuration
|
|
type 1 is available. how about type 2 ?*/
|
|
if (raw_pci_ops)
|
|
return is_mmconf_reserved(e820__mapped_all, cfg, dev, 1);
|
|
|
|
return false;
|
|
}
|
|
|
|
static void __init pci_mmcfg_reject_broken(int early)
|
|
{
|
|
struct pci_mmcfg_region *cfg;
|
|
|
|
list_for_each_entry(cfg, &pci_mmcfg_list, list) {
|
|
if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
|
|
pr_info(PREFIX "not using MMCONFIG\n");
|
|
free_all_mmcfg();
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
|
|
struct acpi_mcfg_allocation *cfg)
|
|
{
|
|
if (cfg->address < 0xFFFFFFFF)
|
|
return 0;
|
|
|
|
if (!strncmp(mcfg->header.oem_id, "SGI", 3))
|
|
return 0;
|
|
|
|
if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010))
|
|
return 0;
|
|
|
|
pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
|
|
"is above 4GB, ignored\n", cfg->pci_segment,
|
|
cfg->start_bus_number, cfg->end_bus_number, cfg->address);
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int __init pci_parse_mcfg(struct acpi_table_header *header)
|
|
{
|
|
struct acpi_table_mcfg *mcfg;
|
|
struct acpi_mcfg_allocation *cfg_table, *cfg;
|
|
unsigned long i;
|
|
int entries;
|
|
|
|
if (!header)
|
|
return -EINVAL;
|
|
|
|
mcfg = (struct acpi_table_mcfg *)header;
|
|
|
|
/* how many config structures do we have */
|
|
free_all_mmcfg();
|
|
entries = 0;
|
|
i = header->length - sizeof(struct acpi_table_mcfg);
|
|
while (i >= sizeof(struct acpi_mcfg_allocation)) {
|
|
entries++;
|
|
i -= sizeof(struct acpi_mcfg_allocation);
|
|
}
|
|
if (entries == 0) {
|
|
pr_err(PREFIX "MMCONFIG has no entries\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
|
|
for (i = 0; i < entries; i++) {
|
|
cfg = &cfg_table[i];
|
|
if (acpi_mcfg_check_entry(mcfg, cfg)) {
|
|
free_all_mmcfg();
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
|
|
cfg->end_bus_number, cfg->address) == NULL) {
|
|
pr_warn(PREFIX "no memory for MCFG entries\n");
|
|
free_all_mmcfg();
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_ACPI_APEI
|
|
extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
|
|
void *data), void *data);
|
|
|
|
static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
|
|
void *data), void *data)
|
|
{
|
|
struct pci_mmcfg_region *cfg;
|
|
int rc;
|
|
|
|
if (list_empty(&pci_mmcfg_list))
|
|
return 0;
|
|
|
|
list_for_each_entry(cfg, &pci_mmcfg_list, list) {
|
|
rc = func(cfg->res.start, resource_size(&cfg->res), data);
|
|
if (rc)
|
|
return rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
|
|
#else
|
|
#define set_apei_filter()
|
|
#endif
|
|
|
|
static void __init __pci_mmcfg_init(int early)
|
|
{
|
|
pci_mmcfg_reject_broken(early);
|
|
if (list_empty(&pci_mmcfg_list))
|
|
return;
|
|
|
|
if (pcibios_last_bus < 0) {
|
|
const struct pci_mmcfg_region *cfg;
|
|
|
|
list_for_each_entry(cfg, &pci_mmcfg_list, list) {
|
|
if (cfg->segment)
|
|
break;
|
|
pcibios_last_bus = cfg->end_bus;
|
|
}
|
|
}
|
|
|
|
if (pci_mmcfg_arch_init())
|
|
pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
|
|
else {
|
|
free_all_mmcfg();
|
|
pci_mmcfg_arch_init_failed = true;
|
|
}
|
|
}
|
|
|
|
static int __initdata known_bridge;
|
|
|
|
void __init pci_mmcfg_early_init(void)
|
|
{
|
|
if (pci_probe & PCI_PROBE_MMCONF) {
|
|
if (pci_mmcfg_check_hostbridge())
|
|
known_bridge = 1;
|
|
else
|
|
acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
|
|
__pci_mmcfg_init(1);
|
|
|
|
set_apei_filter();
|
|
}
|
|
}
|
|
|
|
void __init pci_mmcfg_late_init(void)
|
|
{
|
|
/* MMCONFIG disabled */
|
|
if ((pci_probe & PCI_PROBE_MMCONF) == 0)
|
|
return;
|
|
|
|
if (known_bridge)
|
|
return;
|
|
|
|
/* MMCONFIG hasn't been enabled yet, try again */
|
|
if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
|
|
acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
|
|
__pci_mmcfg_init(0);
|
|
}
|
|
}
|
|
|
|
static int __init pci_mmcfg_late_insert_resources(void)
|
|
{
|
|
struct pci_mmcfg_region *cfg;
|
|
|
|
pci_mmcfg_running_state = true;
|
|
|
|
/* If we are not using MMCONFIG, don't insert the resources. */
|
|
if ((pci_probe & PCI_PROBE_MMCONF) == 0)
|
|
return 1;
|
|
|
|
/*
|
|
* Attempt to insert the mmcfg resources but not with the busy flag
|
|
* marked so it won't cause request errors when __request_region is
|
|
* called.
|
|
*/
|
|
list_for_each_entry(cfg, &pci_mmcfg_list, list)
|
|
if (!cfg->res.parent)
|
|
insert_resource(&iomem_resource, &cfg->res);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Perform MMCONFIG resource insertion after PCI initialization to allow for
|
|
* misprogrammed MCFG tables that state larger sizes but actually conflict
|
|
* with other system resources.
|
|
*/
|
|
late_initcall(pci_mmcfg_late_insert_resources);
|
|
|
|
/* Add MMCFG information for host bridges */
|
|
int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
|
|
phys_addr_t addr)
|
|
{
|
|
int rc;
|
|
struct resource *tmp = NULL;
|
|
struct pci_mmcfg_region *cfg;
|
|
|
|
if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
|
|
return -ENODEV;
|
|
|
|
if (start > end)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&pci_mmcfg_lock);
|
|
cfg = pci_mmconfig_lookup(seg, start);
|
|
if (cfg) {
|
|
if (cfg->end_bus < end)
|
|
dev_info(dev, FW_INFO
|
|
"MMCONFIG for "
|
|
"domain %04x [bus %02x-%02x] "
|
|
"only partially covers this bridge\n",
|
|
cfg->segment, cfg->start_bus, cfg->end_bus);
|
|
mutex_unlock(&pci_mmcfg_lock);
|
|
return -EEXIST;
|
|
}
|
|
|
|
if (!addr) {
|
|
mutex_unlock(&pci_mmcfg_lock);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rc = -EBUSY;
|
|
cfg = pci_mmconfig_alloc(seg, start, end, addr);
|
|
if (cfg == NULL) {
|
|
dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
|
|
rc = -ENOMEM;
|
|
} else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
|
|
dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
|
|
&cfg->res);
|
|
} else {
|
|
/* Insert resource if it's not in boot stage */
|
|
if (pci_mmcfg_running_state)
|
|
tmp = insert_resource_conflict(&iomem_resource,
|
|
&cfg->res);
|
|
|
|
if (tmp) {
|
|
dev_warn(dev,
|
|
"MMCONFIG %pR conflicts with "
|
|
"%s %pR\n",
|
|
&cfg->res, tmp->name, tmp);
|
|
} else if (pci_mmcfg_arch_map(cfg)) {
|
|
dev_warn(dev, "fail to map MMCONFIG %pR.\n",
|
|
&cfg->res);
|
|
} else {
|
|
list_add_sorted(cfg);
|
|
dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
|
|
&cfg->res, (unsigned long)addr);
|
|
cfg = NULL;
|
|
rc = 0;
|
|
}
|
|
}
|
|
|
|
if (cfg) {
|
|
if (cfg->res.parent)
|
|
release_resource(&cfg->res);
|
|
kfree(cfg);
|
|
}
|
|
|
|
mutex_unlock(&pci_mmcfg_lock);
|
|
|
|
return rc;
|
|
}
|
|
|
|
/* Delete MMCFG information for host bridges */
|
|
int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
|
|
{
|
|
struct pci_mmcfg_region *cfg;
|
|
|
|
mutex_lock(&pci_mmcfg_lock);
|
|
list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
|
|
if (cfg->segment == seg && cfg->start_bus == start &&
|
|
cfg->end_bus == end) {
|
|
list_del_rcu(&cfg->list);
|
|
synchronize_rcu();
|
|
pci_mmcfg_arch_unmap(cfg);
|
|
if (cfg->res.parent)
|
|
release_resource(&cfg->res);
|
|
mutex_unlock(&pci_mmcfg_lock);
|
|
kfree(cfg);
|
|
return 0;
|
|
}
|
|
mutex_unlock(&pci_mmcfg_lock);
|
|
|
|
return -ENOENT;
|
|
}
|